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| 型號(hào)： | MC92604ZT |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 22/122頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX ETH DUAL GIG 196-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 630 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 2/2 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
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MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Glossary-2
Freescale Semiconductor
Inter Symbol Interference (ISI). A distortion caused by the high-frequency loss
characteristics of the transmission media.
L
Least-significant bit (lsb). The bit of the least value in an address, register, data element, or
instruction encoding.
M
Media access controller (MAC). The data link sublayer that is responsible for transferring
data to and from the physical layer.
N
Negated. Indicates inactive state of signal has been set. Refers to either inputs or outputs.
P
Physical coding sublayer (PCS). PCS is defined as part of a sublayer in the IEEE Std.
802.3-2002 [4]. The PCS sublayer encodes data bits into code-groups that can be
transmitted over the physical medium. It is used to couple the gigabit media independent
interface (GMII) and a physical medium attachment (PMA).
Phase Locked Loop (PLL).
Physical medium attachment (PMA) sublayer. The PMA is defined as part of a sublayer in
the IEEE Std. 802.3-2002 [4]. The PMA is part of the physical layer that provides
transmission, reception, collision detection, clock recovery, and skew alignment.
Parts per million (ppm).
R
Reduced Gigabit Media Independent Interface (RGMII). The reduced interface between
the reconciliation sublayer and the physical coding sublayer (PCS). The interface is
reduced from 8-bit wide to 4-bit wide and data transfer is DDR.
Reduced Ten Bit Interface (RTBI). The reduced interface between the reconciliation sublayer
and the physical coding sublayer (PCS).The interface is reduced from 10-bit wide to 5-bit
wide and data transfer is DDR.
Running disparity. The amount of DC imbalance over a history of symbols transmitted over
a link. Equal to the difference between the number of one and zero symbols transmitted.
SSerDes. Serializer/deserializer.
Symbol. One piece of information sent across the link; different from a bit in that bit implies
data where symbol is encoded data.
T
Ten bit interface physical layer (TBI PHY) interface.
W
Word synchronization. Alignment of two or more receivers’ data by adjusting for differences
in media and systemic delay between them such that data is presented by the receivers in
the same grouping as they were transmit.
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