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參數(shù)資料
| 型號(hào)： | MC92604ZT |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 42/122頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX ETH DUAL GIG 196-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 630 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 2/2 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
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Transmitter
MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1
2-4
Freescale Semiconductor
2.3
Transmitter Interface Configuration
The transmitter may operate in one of eight data interface configurations as shown in Table 2-2. The
compatibility configuration pin, COMPAT, establishes operation in either the backplane applications mode
or the Ethernet compatible mode. The 10-bit interface enable, TBIE, configuration input, determines if the
internal 8B/10B encoder will be used with uncoded input data or bypassed for a pre-encoded (coded) input
data. When the DDR configuration pin is enabled, it reduces the interface from an 8-/10-bit single data rate
interface to a 4-/5-bit double data rate interface.
The configuration signals, COMPAT and TBIE, also affect the receiver’s configuration.
Transmit data is sampled and stored in the input FIFO on the rising edge (single data rate) of the
appropriate transmit clock, if DDR is low, or both edges (double data rate) of the transmit clock if DDR is
high. The FIFO accepts data to be transmitted and synchronizes it to the internal clock domain.
The 8B/10B encoder takes an 8-bit data/control from the input register and encodes it into 10-bit
transmission characters. The fibre channel 8B/10B coding standard is followed [1,2]. A detailed
TST_1, TST_0
Test mode config inputs
Decoded to define various test modes (see
” for details)
Input
—
MEDIA
Media impedance select
Indicates the impedance of the transmission media.
Low indicates 50
and high indicates 75 .
Input
—
XLINK_x_N/
XLINK_x_P
Link serial transmit data
Differential serial transmit data output pads
Output
—
Internal Signals
rx_clock
High-speed transceiver
clock
Internal, differential high speed clock used to
transmit and receive link data
Input
—
repeat_data
Received repeat data
Repeater mode, received data to re-transmit
Input
—
loop_back_data
Loopback data
Differential loopback transmit data
Output
—
auto_neg_enable
Auto-negotiation enable
Auto-negotiate is enabled if this signal is high and in
GMII mode
Input
High
Table 2-2. MC92604 Data Interface Modes
Data Interface Mode
COMPAT
TBIE
DDR
Backplane 8-bit uncoded data
Low
Backplane (4-bit reduced interface) uncoded data
Low
High
Backplane 10-bit coded data
Low
High
Low
Backplane (5-bit reduced interface) coded data
Low
High
Ethernet compatible GMII
High
Low
Ethernet compatible RGMII
High
Low
High
Ethernet compatible TBI
High
Low
Ethernet compatible RTBI
High
Table 2-1. MC92604 Transmitter Interface Signals (continued)
Signal Name
Description
Function
Direction
Active
State
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