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| 型號： | MC92604ZT |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 80/122頁 |
| 文件大小： | 0K |
| 描述： | IC TXRX ETH DUAL GIG 196-MAPBGA |
| 標準包裝： | 630 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 2/2 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應商設備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
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Management Interface (MDIO)
MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1
4-4
Freescale Semiconductor
4.2.2
MDIO RA 1—Status Register
Figure 4-2 shows the format for the status register, MDIO RA 1, in the MC92604. The status register is a
read-only register.
Table 4-3 lists the corresponding field descriptions for the status register.
15
14
13
12
11
10
9
8
R
100BASE-
T4
100BASE-X
Full-Duplex
100BASE-X
Half -Duplex
10 Mb/s
Full-
Duplex
10 Mb/s
Half-
Duplex
100BASE-
T2
Full-Duplex
100BASE-
T2 Half-Duplex
Extended
Status
W
Reset
0
1
7
6
5
4
3
2
1
0
R
Reserved
MF
Preamble
Suppress
Auto-
Negotiation
Complete
Remote
Fault
Auto-
Negotiation
Ability
Link
Status
Jabber Detect
Extended
Capability
W
Reset
0
0/1
0
1
Figure 4-2. Status Register (MDIO RA 1)
Table 4-3. Status Register (MDIO RA 1) Field Descriptions
Bits
Name
Description1
15
100BASE-T4
Bit 15 is forced to zero and may not be modified. MC92604 does not support 100BASE-T4
operation. (R)
14
100BASE-X
full-duplex
Bit 14 is forced to zero and may not be modified. MC92604 does not support 100BASE-X
operation. (R)
13
100BASE-X
half -duplex
Bit 13 is forced to zero and may not be modified. MC92604 does not support 100BASE-X
operation. (R)
12
10 Mb/s
full-duplex
Bit 12 is forced to zero and may not be modified. MC92604 does not support
100BASE-10 Mb/s operation. (R)
11
10 Mb/s
half-duplex
Bit 11 is forced to zero and may not be modified. MC92604 does not support
100BASE-10 Mb/s operation. (R)
10
100BASE-T2
full-duplex
Bit 10 is forced to zero and may not be modified. MC92604 does not support 100BASE-T2
operation. (R)
9
100BASE-T2
half-duplex
Bit 9 is forced to zero and may not be modified. MC92604 does not support 100BASE-T2
operation. (R)
Extended status
Bit 8 is forced to one and may not be modified. MC92604 supports extended status operation.
Extended status information is available in MDIO RA 15. (R)
7
Reserved
Bit 7 is forced to zero and may not be modified. (R)
6
MF preamble
suppression
Bit 6 is forced to zero and may not be modified. The MC92604 implementation of the MDIO
protocol requires a preamble for the management frames. (R)
5
Auto-negotiation
complete
Bit 5 is initialized to zero This bit is set when the channel has successfully completed the AN
sequence. This bit is cleared when read. (R, SC)
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