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參數(shù)資料
| 型號： | MC92604ZT |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 76/122頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX ETH DUAL GIG 196-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 630 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 2/2 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
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MC92604 Dual Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Freescale Semiconductor
4-1
Chapter 4
Management Interface (MDIO)
This chapter consists of the following sections:
The management data input/output (MDIO) interface as defined in Clause 22 of IEEE Std. 802.3-2002 [4]
is supported by the MC92604 Dual Gigabit Ethernet transceiver. Details for protocol and electrical
characteristics are available in the standard.
This chapter provides details on the MDIO interface signals and their associated registers. The MDIO is
accessible in all of the backplane or Ethernet compatibility operational modes.
4.1
MDIO Interface
The MC92604 chip MDIO interface consists of one enable input, five address inputs, one clock input, and
one bidirectional data signal.
Some users may wish to use the MDIO interface, and others may not. If the MDIO interface is to be used
then the MDIO enable input, MDIO_EN, must be asserted high. The MDIO interface is available whether
COMPAT is enabled or not.
On power up, the MC92604 will always assume the default configuration defined by the pins of the device.
The configuration can then be changed through the MDIO interface regardless of the application operating
mode. If MDIO is not used (MDIO_EN is low), the MC92604 will operate in the default configuration.
The MDIO interface is a multidrop serial interface and each part must have a unique PHY address. Each
channel is addressed separately in the MC92604. The base address to each transceiver must be mod 2. This
address is read from four input pins that must be externally pulled up or pulled down to furnish a unique
address for each part that is connected to a MDIO bus. These four address inputs are identified as:
MD_ADR4, MD_ADR3, MD_ADR2, and MD_ADR1.
The least significant bit of the 5-bit address, MD_ADR0, is used to uniquely identify each MC92604
channel (0 indicates channel A, 1 indicates channel B).
The 2.5-MHz data interface clock, MD_CLK, is sourced at the MDIO master (MAC) and is used by each
slave MDIO device. The MC92604 is designed as MDIO slave devices.
The MDIO data signal, MD_DATA, is a bidirectional serial signal used to read and write management data
from/to the MDIO registers.
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