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參數(shù)資料
| 型號： | MC68HC916X1CTH16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120 |
| 封裝： | QFP-120 |
| 文件頁數(shù)： | 97/172頁 |
| 文件大?。?/td> | 1200K |
| 代理商： | MC68HC916X1CTH16 |
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MOTOROLA
MC68HC916X1
30
MC68HC916X1TS/D
3.6.2 Address Bus
Address bus signals ADDR[19:0] define the address of the most significant byte to be transferred
during a bus cycle. The MCU places the address on the bus at the beginning of a bus cycle. The
address is valid while AS is asserted. The CPU16 drives ADDR[23:20] to the same logic state as
ADDR19.
3.6.3 Address Strobe
AS is a timing signal that indicates the validity of an address on the address bus and of many control
signals. It is asserted one-half clock after the beginning of a bus cycle.
3.6.4 Data Bus
Data bus signals DATA[15:0] comprise a bidirectional, non-multiplexed parallel bus that transfers
data to or from the MCU. A read or write operation can transfer 8 or 16 bits of data in one bus cycle.
During a read cycle, the data is latched by the MCU on the last falling edge of the clock for that bus
cycle. For a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand
size. The MCU places the data on the data bus one-half clock cycle after AS is asserted in a write
cycle.
3.6.5 Data Strobe
Data strobe (DS) is a timing signal. For a read cycle, the MCU asserts DS to signal an external de-
vice to place data on the bus. DS is asserted at the same time as AS during a read cycle. For a
write cycle, DS signals an external device that data on the bus is valid. The MCU asserts DS one
full clock cycle after the assertion of AS during a write cycle.
3.6.6 Bus Cycle Termination Signals
During bus cycles, external devices assert a data transfer and size acknowledge signal (DSACK1).
During a read cycle, the signal tells the MCU to terminate the bus cycle and to latch data. During a
write cycle, the signal indicates that an external device has successfully stored data and that the
cycle can terminate. The DSACK1 signal also indicates to the MCU the size of the port for the bus
cycle just completed. In the MC68HC916X1, the DSACK0 pin is not provided and an external de-
vice indicates the availability of data by asserting DSACK1 regardless of port size.
The bus error (BERR) signal is also a bus cycle termination indicator and can be used in the ab-
sence of DSACK1 to indicate a bus error condition. BERR can also be asserted in conjunction with
DSACK1, provided BERR meets the appropriate timing requirements. The internal bus monitor can
be used to generate the BERR signal for internal and internal-to-external transfers. When BERR is
asserted, the CPU16 takes a bus error exception.
3.6.7 Data Transfer Mechanism
MCU architecture supports byte, word, and long-word operands, allowing access to 8- and 16-bit
data ports through the use of asynchronous cycles.
The MCU always attempts to transfer the maximum amount of data on all bus cycles. For a word
operation, it is assumed that the port is 16 bits wide when the bus cycle begins. Operand bytes are
designated as shown in Figure 9. OP0 is the most significant byte of a long-word operand, and OP3
is the least significant byte. The two bytes of a word-length operand are OP0 (most significant) and
OP1. The single byte of a byte-length operand is OP0.
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