參數(shù)資料
型號(hào)： MC68HC916X1CTH16
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
封裝： QFP-120
文件頁數(shù)： 20/172頁
文件大?。?/td> 1200K
代理商： MC68HC916X1CTH16
MOTOROLA
MC68HC916X1
116
MC68HC916X1TS/D
SCCR1 contains SCI configuration parameters. The CPU can read and write this register at any
time. The SCI can modify RWU in some circumstances. In general, interrupts enabled by these con-
trol bits are cleared by reading SCSR, then reading (for receiver status bits) or writing (for transmit-
ter status bits) SCDR.
Bit 15 — Not Implemented
LOOPS — Loop Mode
0 = Normal SCI operation, no looping, feedback path disabled
1 = Test SCI operation, looping, feedback path enabled
LOOPS controls a feedback path on the data serial shifter. When loop mode is enabled, SCI transmitter
output is fed back into the receive serial shifter. TXD is asserted (idle line). Both transmitter and receiver
must be enabled before entering loop mode.
WOMS — Wired-OR Mode for SCI Pins
0 = If configured as an output, TXD is a normal CMOS output.
1 = If configured as an output, TXD is an open-drain output.
WOMS determines whether the TXD pin is an open-drain output or a normal CMOS output. This bit is
used only when TXD is an output. If TXD is used as a general-purpose input pin, WOMS has no effect.
ILT — Idle-Line Detect Type
0 = Short idle-line detect (start count on first one)
1 = Long idle-line detect (start count on first one after stop bit(s))
PT — Parity Type
0 = Even parity
1 = Odd parity
When parity is enabled, PT determines whether parity is even or odd for both the receiver and the trans-
mitter.
PE — Parity Enable
0 = SCI parity disabled
1 = SCI parity enabled
PE determines whether parity is enabled or disabled for both the receiver and the transmitter. If the re-
ceived parity bit is not correct, the SCI sets the PF error flag in SCSR.
When PE is set, the most significant bit (MSB) of the data field is used for the parity function, which re-
sults in either seven or eight bits of user data, depending on the condition of M bit. Table 62 lists the
available choices.
SCCR1 — SCI Control Register 1
$YFFC0A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LOOPS WOMS ILT
PT
PE
M
WAKE TIE
TCIE
RIE
ILIE
TE
RE
RWU SBK
RESET:
0
Table 62 Parity Enable Data Bit Selection
M
PE
Result
0
8 Data Bits
0
1
7 Data Bits, 1 Parity Bit
1
0
9 Data Bits
1
8 Data Bits, 1 Parity Bit
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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