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| 型號： | MC68HC916X1CTH16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120 |
| 封裝： | QFP-120 |
| 文件頁數(shù)： | 147/172頁 |
| 文件大小： | 1200K |
| 代理商： | MC68HC916X1CTH16 |
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MOTOROLA
MC68HC916X1
76
MC68HC916X1TS/D
4.7.2 Exception Stack Frame
During exception processing, the contents of the program counter and condition code register are
stacked at a location pointed to by SK:SP. Unless it is altered during exception processing, the
stacked PK:PC value is the address of the next instruction in the current instruction stream, plus
$0006. Figure 12 shows the exception stack frame.
Figure 12 Exception Stack Frame Format
4.7.3 Exception Processing Sequence
Exception processing is performed in four phases.
A. Priority of all pending exceptions is evaluated, and the highest priority exception is pro-
cessed first.
B. Processor state is stacked, then the CCR PK extension field is cleared.
C. An exception vector number is acquired and converted to a vector address.
D. The content of the vector address is loaded into the PC, and the processor jumps to the
exception handler routine.
There are variations within each phase for differing types of exceptions. However, all vectors but
the reset vectors contain 16-bit addresses, and the PK field is cleared. Exception handlers must be
located within bank 0 or vectors must point to a jump table.
4.7.4 Types of Exceptions
Exceptions can be either internally or externally generated. External exceptions, which are defined
as asynchronous, include interrupts, bus errors (BERR), breakpoints (BKPT), and resets (RESET).
Internal exceptions, which are defined as synchronous, include the software interrupt (SWI) instruc-
tion, the background (BGND) instruction, illegal instruction exceptions, and the divide-by-zero ex-
ception.
4.7.4.1 Asynchronous Exceptions
Asynchronous exceptions occur without reference to CPU16 or IMB clocks, but exception process-
ing is synchronized. For all asynchronous exceptions but RESET, exception processing begins at
the first instruction boundary following recognition of an exception.
Because of pipelining, the stacked return PK : PC value for all asynchronous exceptions, other than
reset, is equal to the address of the next instruction in the current instruction stream plus $0006.
The RTI instruction, which must terminate all exception handler routines, subtracts $0006 from the
stacked value to resume execution of the interrupted instruction stream.
4.7.4.2 Synchronous Exceptions
Synchronous exception processing is part of an instruction definition. Exception processing for syn-
chronous exceptions is always completed, and the first instruction of the handler routine is always
executed, before interrupts are detected.
High Address
SP After Exception Stacking
Condition Code Register
High Address
Program Counter
SP Before Exception Stacking
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For More Information On This Product,
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