參數(shù)資料
型號: MC68HC916X1CTH16
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
封裝: QFP-120
文件頁數(shù): 7/172頁
文件大小: 1200K
代理商: MC68HC916X1CTH16
MOTOROLA
MC68HC916X1
104
MC68HC916X1TS/D
PORTQS latches I/O data. Writes drive pins defined as outputs. Reads return data present on the
pins. To avoid driving undefined data, first write a byte to PORTQS, then configure DDRQS.
Clearing a bit in PQSPAR assigns the corresponding pin to general-purpose I/O; setting a bit as-
signs the pin to the QSPI. PQSPAR does not affect operation of the SCI. Table 55 displays PQS-
PAR pin assignments.
DDRQS determines whether pins are inputs or outputs. Clearing a bit makes the corresponding pin
an input; setting a bit makes the pin an output. DDRQS affects both QSPI function and I/O function.
Table 56 shows the effect of DDRQS on QSM pin functions.
1. PQS2 is a digital I/O pin unless the SPI is en-
abled (SPE in SPCR1 set), in which case it be-
comes SPI serial clock SCK.
2. PQS7 is a digital I/O pin unless the SCI trans-
mitter is enabled (TE in SCCR1 = 1), in which
case it becomes SCI serial output TXD.
PORTQS — Port QS Data Register
$YFFC14
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
PQS7 PQS6 PQS5 PQS4 PQS3 PQS2 PQS1 PQS0
RESET:
0
PQSPAR — PORT QS Pin Assignment Register
$YFFC16
DDRQS — PORT QS Data Direction Register
$YFFC17
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0 PQSPA6 PQSPA5 PQSPA4 PQSPA3 0 PQSPA1 PQSPA0 DDQS7 DDQS6 DDQS5 DDQS4 DDQS3 DDQS2 DDQS1 DDQS0
RESET:
0
Table 55 PQSPAR Pin Assignments
PQSPAR Field
PQSPAR Bit
Pin Function
PQSPA0
0
PQS0
1
MISO
PQSPA1
0
PQS1
1
MOSI
PQS21
SCK
PQSPA3
0
PQS3
1
PCS0/SS
PQSPA4
0
PQS4
1
PCS1
PQSPA5
0
PQS5
1
PCS2
PQSPA6
0
PQS6
1
PCS3
PQS72
TXD
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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