參數(shù)資料
型號： MC68HC916X1CTH16
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
封裝： QFP-120
文件頁數(shù)： 154/172頁
文件大?。?/td> 1200K
代理商： MC68HC916X1CTH16
MOTOROLA
MC68HC916X1
82
MC68HC916X1TS/D
PADA[5:0] — Port ADA Data Pins
A read of PADA[5:0] returns the logic level of the port ADA pins. If an input is not at an appropriate logic
level (i.e. outside the defined levels), the read is indeterminate. Use of a port ADA pin for digital input
does not preclude use as an analog input.
ADCTL0 is used to select ADC clock source and to set up prescaling. Writes to it have immediate
effect.
RES10 — 10-Bit Resolution
0 = 8-bit resolution
1 = 10-bit resolution
Conversion results are appropriately aligned in result registers to reflect conversion status.
STS[1:0] — Sample Time Select
Total conversion time depends on initial sample time, transfer time, final sample time, and resolution
time. Initial sample time is fixed at two clocks. Transfer time is fixed at two clocks. Resolution time is
fixed at 10 ADC clock cycles for an 8-bit conversion and 12 ADC clock cycles for a 10-bit conversion.
Final sample time depends on the STS[1:0] field. Refer to Table 40.
PRS[4:0] — Prescaler Rate Selection Field
The ADC clock is generated from the system clock using a modulo counter and a divide-by-two circuit.
The binary value of this field is the counter modulus. System clock is divided by the PRS[4:0] value plus
one, then sent to the divide-by-two circuit. Refer to Table 41.
ADCTL0 — A/D Control Register 0
$YFF70A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
RES10
STS[1:0]
PRS[4:0]
RESET:
0
1
Table 40 Sample Time Select Field
STS[1:0]
Sample Time
00
2 A/D Clock Periods
01
4 A/D Clock Periods
10
8 A/D Clock Periods
11
16 A/D Clock Periods
Table 41 Prescaler Rate Selection Field
PRS[4:0]
Divisor Value
00000
4
00001
4
00010
6
...
11101
60
11110
62
11111
64
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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