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參數(shù)資料
| 型號(hào)： | MC68HC916X1CTH16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120 |
| 封裝： | QFP-120 |
| 文件頁(yè)數(shù)： | 44/172頁(yè) |
| 文件大小： | 1200K |
| 代理商： | MC68HC916X1CTH16 |
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MOTOROLA
MC68HC916X1
138
MC68HC916X1TS/D
If the state of the STOP shadow bit is one, or data bus pin DATA15 is pulled low during reset, the
STOP bit in BFEMCR is set during reset and the BEFLASH array is disabled. The module does not
respond to array or bootstrap vector accesses until the STOP bit is cleared. This allows an external
device to respond to accesses to the BEFLASH array address space or to bootstrap accesses. The
erased state of the shadow bits is one. An erased module comes out of reset in STOP mode.
10.5.2 Bootstrap Operation
After reset, the CPU16 begins bootstrap operation by fetching initial values for its internal registers
from IMB addresses $000000 through $000006 in program space. These are the addresses of the
bootstrap vectors in the exception vector table. If BOOT = 0 and STOP = 0 in BFEMCR during reset,
the BEFLASH module is configured to respond to bootstrap vector accesses. Vector assignments
are shown in Table 72.
As soon as address $000006 has been read, BEFLASH operation returns to normal, and the mod-
ule no longer responds to bootstrap vector accesses.
10.5.3 Normal Operation
The BEFLASH module allows a byte or aligned-word read in one bus cycle. Long-word reads re-
quire two bus cycles.
The module checks function codes to verify address space access type. Array accesses are de-
fined by the state of ASPC[1:0] in BFEMCR.
10.5.4 Program/Erase Operation
An unprogrammed flash bit has a logic state of one. A bit must be programmed to change its state
from one to zero. Erasing a bit returns it to a logic state of one. Programming or erasing the BE-
FLASH array requires a series of control register writes and a write to an array address. The same
procedure is used to program control registers that contain flash bits. Programming is restricted to
a single byte or aligned word at a time. Erasure of BEFLASH array blocks and control shadow bits
are dependent on the setting of ADDR[3:1] of the address written to during an erase operation. Re-
fer to Table 71 for the address bit patterns corresponding to specific BEFLASH blocks.
NOTE
In order to program the array, programming voltage must be applied to the VFPE2K
pin. VFPE2K ≥ (VDD 0.3 V) must be applied at all times or damage to the BEFLASH
module can occur.
Refer to 11 Electrical Characteristics for information on programming and erasing specifications
for the BEFLASH module.
10.5.4.1 Programming Sequence
Table 72 Bootstrap Vector Assignments
EEPROM Bootstrap Word
IMB Vector Address
MCU Reset Vector Content
BFEBS0
$000000
Initial ZK, SK, and PK
BFEBS1
$000002
Initial PC
BFEBS2
$000004
Initial SP
BFEBS3
$000006
Initial IZ
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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