參數(shù)資料
型號： MC68HC916X1CTH16
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
封裝： QFP-120
文件頁數(shù)： 94/172頁
文件大?。?/td> 1200K
代理商： MC68HC916X1CTH16
MOTOROLA
MC68HC916X1
28
MC68HC916X1TS/D
3.4.2 Halt Monitor
The halt monitor responds to an assertion of HALT on the internal bus, caused by a double bus
fault. This signal is asserted by the CPU after a double bus fault occurs. A flag in the reset status
register (RSR) indicates that the last reset was caused by the halt monitor. The halt monitor reset
can be inhibited by the HME bit in the SYPCR.
3.4.3 Spurious Interrupt Monitor
The spurious interrupt monitor causes a bus error exception if no interrupt arbitration occurs during
an interrupt acknowledge cycle. The most common cause of spurious interrupts is failure to set the
module configuration register IARB[3:0] to a non-zero value for modules that can generate inter-
rupts.
3.4.4 Software Watchdog
The software watchdog service register (SWSR) is controlled by SWE in SYPCR. Once enabled,
the watchdog requires that a service sequence be written to SWSR on a periodic basis. If servicing
does not take place, the watchdog times out and issues a reset. This register can be written at any
time, but returns zeros when read.
Each time the service sequence is written, the software watchdog timer restarts. The sequence to
restart consists of the following steps:
Write $55 to SWSR
Write $AA to SWSR
Both writes must occur before timeout in the order listed, but any number of instructions, up to the
end of the timeout period, can be executed between the two writes.
Watchdog clock rate is affected by SWP and SWT[1:0] in SYPCR.
When SWT[1:0] are modified, a watchdog service sequence must be performed before the new
time-out period will take effect.
The reset value of SWP is the complement of the state of the MODCLK pin on the rising edge of
reset.
Software watchdog time-out period is given in the following equation:
3.5 External Bus Interface
The external bus interface (EBI) transfers information between the internal MCU bus and external
devices when the MCU is operating in expanded modes. In 16-bit expanded mode, the external bus
has 24 address lines and 16 data lines. In 8-bit expanded mode, the external bus has 24 address
lines and 8 data lines. Because the CPU16 drives only 20 of the 24 IMB address lines, ADDR[23:20]
follow the output state of ADDR19.
SWSR — Software Watchdog Service Register
$YFFA27
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
UNUSED
SWSR
RESET:
0
Timeout Period
Divide Ratio Specified by SWP and SWT[1:0]
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關PDF資料
PDF描述
MC916X1CTH16B1 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
SPMC916X1CTH16 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
MC68HCL05J1ADWR2 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20
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