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參數(shù)資料
| 型號(hào)： | MC68HC916X1CTH16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120 |
| 封裝： | QFP-120 |
| 文件頁數(shù)： | 101/172頁 |
| 文件大?。?/td> | 1200K |
| 代理商： | MC68HC916X1CTH16 |
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MOTOROLA
MC68HC916X1
34
MC68HC916X1TS/D
3.7.4 Power-On Reset
When the SCIM clock synthesizer is used to generate system clocks, power-on reset involves spe-
cial circumstances related to the application of system and clock synthesizer power. Regardless of
clock source, voltage must be applied to the clock synthesizer power input pin VDDSYN, so that the
MCU can operate. The following discussion assumes that VDDSYN is applied before and during re-
set. This minimizes crystal start-up time. When VDDSYN is applied at power-on, start-up time is af-
fected by specific crystal parameters and by oscillator circuit design. VDD ramp-up time also affects
pin state during reset.
During power-on reset, an internal circuit in the SCIM drives the IMB internal and external reset
lines. The circuit releases the internal reset line as VDD ramps up to the minimum specified value,
and SCIM pins are initialized. When VDD reaches the specified minimum value, the clock synthe-
sizer VCO begins operation. Clock frequency ramps up to the specified limp mode frequency. The
external RESET line remains asserted until the clock synthesizer PLL locks and 512 CLKOUT cy-
cles elapse.
The SCIM clock synthesizer provides clock signals to the other MCU modules. After the clock is
running and the internal reset signal is asserted for four clock cycles, these modules reset. VDD
ramp time and VCO frequency ramp time determine how long these four cycles take. Worst case
is approximately 15 milliseconds. During this period, module port pins may be in an indeterminate
state. While input-only pins can be put in a known state by means of external pull-up resistors, ex-
ternal logic on input/output or output-only pins must condition the lines during this time. Active driv-
ers require high-impedance buffers or isolation resistors to prevent conflict.
3.7.5 Use of Three-State Control Pin
Asserting the three-state control (TSC) input causes all MCU output drivers to go to an inactive,
high-impedance condition. Although TSC is an active-high input, it does not have an internal pull-
down and must be tied low when not in use.
TSC must remain asserted for ten system clock cycles for drivers to change state. There are certain
constraints on use of TSC during power-up reset.
When the internal clock synthesizer is used (MODCLK held high during reset), synthesizer ramp-
up time affects how long ten clock cycles take. Worst case is approximately 20 milliseconds from
TSC assertion.
When an external clock signal is applied (MODCLK held low during reset), pins go to high-imped-
ance state as soon after TSC assertion as ten clock pulses have been applied to the EXTAL pin.
NOTE
When TSC assertion takes effect, internal signals are forced to values that can
cause inadvertent mode selection. Once the output drivers change state, the MCU
must be powered down and restarted before normal operation can resume.
3.8 Interrupts
Interrupt recognition and servicing involve complex interaction between the central processing unit,
the single-chip integration module, and a device or module requesting interrupt service.
The CPU16 provides for seven levels of interrupt priority (1–7), seven automatic interrupt vectors,
and 200 assignable interrupt vectors. All interrupts with priorities less than seven can be masked
by the interrupt priority (IP) field in the condition code register. The CPU16 handles interrupts as a
type of asynchronous exception.
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Freescale Semiconductor, Inc.
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