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參數(shù)資料
| 型號(hào)： | MC68HC916X1CTH16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120 |
| 封裝： | QFP-120 |
| 文件頁(yè)數(shù)： | 103/172頁(yè) |
| 文件大?。?/td> | 1200K |
| 代理商： | MC68HC916X1CTH16 |
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MOTOROLA
MC68HC916X1
36
MC68HC916X1TS/D
Each module that can make an interrupt service request, including the SCIM, has an IARB field in
its configuration register. An IARB field can be assigned a value from %0001 (lowest priority) to
%1111 (highest priority). A value of %0000 in an IARB field causes the CPU16 to process a spuri-
ous interrupt exception when an interrupt from that module is recognized.
Because the EBI manages external interrupt requests, the SCIM IARB value is used for arbitration
between internal and external interrupt requests. The reset value of IARB for the SCIM is %1111.
The reset IARB value for all other modules is %0000. Initialization software must assign different
IARB values to implement an arbitration scheme.
Each module must have a unique IARB value. When two or more IARB fields have the same non-
zero value, the CPU16 interprets multiple vector numbers simultaneously, with unpredictable con-
sequences.
Arbitration must always take place, even when a single source requests service. This point is im-
portant for two reasons: the CPU interrupt acknowledge cycle is not driven on the external bus un-
less the SCIM wins contention, and failure to contend causes an interrupt acknowledge bus cycle
to be terminated by a bus error, which causes a spurious interrupt exception to be taken.
When arbitration is complete, the dominant module must place an interrupt vector number on the
data bus and terminate the bus cycle. In the case of an external interrupt request, because the in-
terrupt acknowledge cycle is transferred to the external bus, an external device must decode the
mask value and respond with a vector number, then generate bus cycle termination signals. If the
device does not respond in time, a spurious interrupt exception is taken.
The periodic interrupt timer (PIT) in the SCIM can generate internal interrupt requests of specific
priority at predetermined intervals. By hardware convention, PIT interrupts are serviced before ex-
ternal interrupt service requests of the same priority. Refer to 3.3.4 Periodic Interrupt Timer for
more information.
3.8.2 Interrupt Processing
The following summary outlines the interrupt processing sequence. When the sequence begins, a
valid interrupt service request has been detected and is pending.
A. The CPU finishes higher priority exception processing or reaches an instruction boundary.
B. Processor state is stacked, then the CCR PK extension field is cleared.
C. The interrupt acknowledge cycle begins:
1.
FC[2:0] are driven to %111 (CPU space) encoding.
2.
The address bus is driven as follows. ADDR[23:20] = %1111; ADDR[19:16] = %1111,
which indicates that the cycle is an interrupt acknowledge CPU space cycle; AD-
DR[15:4] = %111111111111; ADDR[3:1] = the priority of the interrupt request being
acknowledged; and ADDR0 = %1.
3.
Request priority is latched into the CCR IP field from the address bus.
D. Modules or external peripherals that have requested interrupt service decode the priority
value on ADDR[3:1]. If request priority is the same as the priority value in the address, IARB
contention takes place. When there is no contention, the spurious interrupt monitor asserts
BERR, and a spurious interrupt exception is processed.
E. After arbitration, the interrupt acknowledge cycle can be completed in one of three ways:
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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