參數(shù)資料
型號(hào)： MC68HC916X1CTH16
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
封裝： QFP-120
文件頁數(shù)： 54/172頁
文件大?。?/td> 1200K
代理商： MC68HC916X1CTH16
MC68HC916X1
MOTOROLA
MC68HC916X1TS/D
147
5. Specification 9A is the worst-case skew between AS and DS or CS. The amount of skew depends on the relative
loading of these signals. When loads are kept within specified limits, skew will not cause AS and DS to fall outside
the limits shown in specification 9.
6. If multiple chip selects are used, CS width negated (specification 15) applies to the time from the negation of a
heavily loaded chip select to the assertion of a lightly loaded chip select. The CS width negated specification be-
tween multiple chip selects does not apply to chip selects being used for synchronous ECLK cycles.
7. Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast
cycle reads. The user is free to use either hold time.
8. Maximum value is equal to (tcyc / 2) + 25 ns.
9. If the asynchronous setup time (specification 47A) requirements are satisfied, the DSACK1 low to data setup time
(specification 31) and DSACK1 low to BERR low setup time (specification 48) can be ignored. The data must
only satisfy the data-in to clock low setup time (specification 27) for the following clock cycle. BERR must satisfy
only the late BERR low to clock low setup time (specification 27A) for the following clock cycle.
10. To ensure coherency during every operand transfer, BG is not asserted in response to BR until after all cycles of
the current operand transfer are complete.
11. In the absence of DSACK1, BERR is an asynchronous input using the asynchronous setup time (specification
47A).
12. After external RESET negation is detected, a short transition period (approximately 2 tcyc) elapses, then the SIM
drives RESET low for 512 tcyc.
13. External logic must pull RESET high during this period in order for normal MCU operation to begin.
14. Eight pipeline states are multiplexed into IPIPE[1:0]. The multiplexed signals have two phases.
15. Address access time = (2.5 + WS) tcyc – tCHAV – tDICL
Chip select access time = (2 + WS) tcyc – tCLSA – tDICL
Where: WS = number of wait states. When fast termination is used (2 clock bus) WS = –1.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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