參數(shù)資料
型號: MC68HC916X1CTH16
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
封裝: QFP-120
文件頁數(shù): 168/172頁
文件大?。?/td> 1200K
代理商: MC68HC916X1CTH16
MC68HC916X1
MOTOROLA
MC68HC916X1TS/D
95
TCNT — Timer Counter Register
$YFF90A
TCNT is the 16-bit free-running counter associated with the input capture, output compare, and
pulse accumulator functions of the GPT module.
PACTL enables the pulse accumulator and selects either event counting or gated mode. In event
counting mode, PACNT is incremented each time an event occurs. In gated mode, it is incremented
by an internal clock.
PAIS — PAI Pin State (Read Only)
PAEN — Pulse Accumulator Enable
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
PAMOD — Pulse Accumulator Mode
0 = External event counting
1 = Gated time accumulation
PEDGE — Pulse Accumulator Edge Control
The effects of PAMOD and PEDGE are shown in Table 46.
PCLKS — PCLK Pin State (Read Only)
I4/O5 — Input Capture 4/Output Compare 5
0 = Output compare 5 enabled
1 = Input capture 4 enabled
PACLK[1:0] — Pulse Accumulator Clock Select (Gated Mode)
Table 47 shows the PACLK[1:0] bit field effects.
PACNT — Pulse Accumulator Counter
Eight-bit read/write counter used for external event counting or gated time accumulation.
PACTL/PACNT — Pulse Accumulator Control Register/Counter
$YFF90C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PAIS PAEN PAMOD PEDGE PCLKS I4/O5
PACLK[1:0]
PULSE ACCUMULATOR COUNTER
RESET:
U
0
Table 46 PAMOD/PEDGE Effects
PAMOD
PEDGE
Effect
0
PAI falling edge increments counter
0
1
PAI rising edge increments counter
1
0
Zero on PAI inhibits counting
1
One on PAI inhibits counting
Table 47 PACLK[1:0] Bit Field
PACLK[1:0]
Pulse Accumulator Clock Selected
00
System clock divided by 512
01
Same clock used to increment TCNT
10
TOF flag from TCNT
11
External clock, PCLK
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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