參數(shù)資料
型號(hào)： MC68HC916X1CTH16
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
封裝： QFP-120
文件頁數(shù)： 3/172頁
文件大?。?/td> 1200K
代理商： MC68HC916X1CTH16
MOTOROLA
MC68HC916X1
100
MC68HC916X1TS/D
7 Queued Serial Module
The QSM contains two serial interfaces, the queued serial peripheral interface (QSPI) and the serial
communication interface (SCI). Figure 19 shows the QSM block diagram.
Figure 19 QSM Block Diagram
7.1 Overview
The QSPI provides peripheral expansion or interprocessor communication through a full-duplex,
synchronous, three-line bus: data in, data out, and a serial clock. Four programmable peripheral
chip-select pins provide addressability for up to 16 peripheral devices. A self-contained RAM queue
allows up to 16 serial transfers of 8 to 16 bits each, or transmission of a 256-bit data stream without
CPU intervention. A special wraparound mode supports continuous sampling of a serial peripheral,
with automatic QSPI RAM updating, which makes the interface to A/D converters more efficient.
The SCI provides a standard nonreturn to zero (NRZ) mark/space format. It operates in either full-
or half-duplex mode. There are separate transmitter and receiver enable bits and dual data buffers.
A modulus-type baud rate generator provides rates from 64 to 524 kbaud with a 16.78 MHz system
clock. Word length of either 8 or 9 bits is software selectable. Optional parity generation and detec-
tion provide either even or odd parity check capability. Advanced error detection circuitry catches
glitches of up to 1/16 of a bit time in duration. Wake-up functions allow the CPU to run uninterrupted
until meaningful data is available.
Table 53 shows the address map of the QSM.
QSPI
INTERFACE
LOGIC
SCI
MISO/PQS0
MOSI/PQS1
SCK/PQS2
PCS0/SS/PQS3
PCS1/PQS4
PCS2/PQS5
PCS3/PQS6
TXD/PQS7
RXD
PORT
QS
QSM BLOCK
IMB
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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