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參數(shù)資料
| 型號： | MC68HC916X1CTH16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120 |
| 封裝： | QFP-120 |
| 文件頁數(shù)： | 88/172頁 |
| 文件大小： | 1200K |
| 代理商： | MC68HC916X1CTH16 |
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MOTOROLA
MC68HC916X1
22
MC68HC916X1TS/D
If a fast reference frequency is provided to the PLL from a source other than a crystal, or an external
system clock signal is applied through the EXTAL pin, the XTAL pin must be left floating.
When an external system clock signal is applied (MODCLK = 0 during reset), the PLL is disabled.
The duty cycle of the input is critical, especially at operating frequencies close to maximum. The
relationship between clock signal duty cycle and clock signal period is expressed as follows:
3.3.2 Clock Synthesizer Operation
VDDSYN is used to power the clock circuits when the system clock is synthesized from either a crys-
tal or an externally supplied reference frequency. A separate power source increases MCU noise
immunity and can be used to run the clock when the MCU is powered down. A quiet power supply
must be used as the VDDSYN source. Adequate external bypass capacitors should be placed as
close as possible to the VDDSYN pin to assure stable operating frequency. When an external system
clock signal is applied and the PLL is disabled, VDDSYN should be connected to the VSS supply.
Refer to the
SCIM Reference Manual (SCIMRM/AD) for more information regarding system clock
power supply conditioning.
A voltage controlled oscillator (VCO) in the PLL generates the system clock signal. To maintain a
50% clock duty cycle, the VCO frequency (fVCO) is either two or four times the system clock fre-
quency, depending on the state of the X bit in SYNCR. The clock signal is fed back to a divider/
counter. The divider controls the frequency of one input to a phase comparator. The other phase
comparator input is a reference signal, either from the crystal oscillator or from an external source.
The comparator generates a control signal proportional to the difference in phase between the two
inputs. This signal is low-pass filtered and used to correct the VCO output frequency.
Filter circuit implementation can vary, depending upon the external environment and required clock
stability. Figure 7 shows a recommended system clock filter network. XFC pin leakage must be
kept as low as possible to maintain optimum stability and PLL performance.
An external filter network connected to the XFC pin is not required when an external system clock
signal is applied and the PLL is disabled (VDDSYN = 0). The XFC pin must be left floating in this case.
Figure 7 System Clock Filter Network
Minimum External Clock Period
Minimum External Clock High/Low Time
50 %
Percentage Variation of External Clock Input Duty Cycle
–
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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16/32 XFC CONN
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