參數(shù)資料
型號(hào)： MC68HC916X1CTH16
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
封裝： QFP-120
文件頁數(shù)： 4/172頁
文件大?。?/td> 1200K
代理商： MC68HC916X1CTH16
MC68HC916X1
MOTOROLA
MC68HC916X1TS/D
101
7.2 Pin Function
Table 54 is a summary of the functions of the QSM pins when they are not configured for general-
purpose I/O. The QSM data direction register (DDRQS) designates each pin except RXD as an in-
put or output.
1. Y = M111, where M is the logic state of the MM bit in the SCIMCR.
Table 53 QSM Address Map
Address
15
8
7
0
$YFFC001
QSM MODULE CONFIGURATION (QSMCR)
$YFFC02
QSM TEST (QTEST)
$YFFC04
QSM INTERRUPT LEVEL (QILR)
QSM INTERRUPT VECTOR (QIVR)
$YFFC06
RESERVED
$YFFC08
SCI CONTROL 0 REGISTER (SCCR0)
$YFFC0A
SCI CONTROL 1 REGISTER (SCCR1)
$YFFC0C
SCI STATUS REGISTER (SCSR)
$YFFC0E
SCI DATA REGISTER (SCDR)
$YFFC10
RESERVED
$YFFC12
RESERVED
$YFFC14
NOT USED
PQS DATA (PORTQS)
$YFFC16
PQS PIN ASSIGNMENT (PQSPAR)
PQS DATA DIRECTION (DDRQS)
$YFFC18
SPI CONTROL 0 REGISTER (SPCR0)
$YFFC1A
SPI CONTROL 1 REGISTER (SPCR1)
$YFFC1C
SPI CONTROL 2 REGISTER (SPCR2)
$YFFC1E
SPI CONTROL 3 REGISTER
(SPCR3)
SPI STATUS REGISTER (SPSR)
$YFFC20–
$YFFCFF
RESERVED
$YFFD00–
$YFFD1F
RECEIVE RAM (RR[0:F])
$YFFD20–
$YFFD3F
TRANSMIT RAM (TR[0:F])
$YFFD40–
$YFFD4F
COMMAND RAM (CR[0:F])
Table 54 QSM Pin Functions
Pin
Mode
Pin Function
MISO
Master
Serial Data Input to QSPI
Slave
Serial Data Output from QSPI
MOSI
Master
Serial Data Output from QSPI
Slave
Serial Data Input to QSPI
SCK
Master
Clock Output from QSPI
Slave
Clock Input to QSPI
PCS0/SS
Master
Input: Assertion Causes Mode Fault
Output: Selects Peripherals
Slave
Input: Selects the QSPI
PCS[3:1]
Master
Output: Selects Peripherals
Slave
None
TXD
Transmit
Serial Data Output from SCI
RXD
Receive
Serial Data Input to SCI
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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