參數(shù)資料
型號(hào)： MC68HC916X1CTH16
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
封裝： QFP-120
文件頁數(shù)： 111/172頁
文件大?。?/td> 1200K
代理商： MC68HC916X1CTH16
MC68HC916X1
MOTOROLA
MC68HC916X1TS/D
43
SPACE[1:0] — Address Space Select
This option field is used to select an address space to be used by the chip select logic. The CPU16 nor-
mally operates in supervisor space. All space types can be used. Interrupt acknowledge cycles take
place in CPU space. Table 29 shows address space bit encodings.
IPL[2:0] — Interrupt Priority Level
When the SPACE[1:0] field is set for CPU space (%00), chip-select logic can be used for interrupt ac-
knowledge. During an interrupt acknowledge cycle, the priority level on address lines ADDR[3:1] is com-
pared to the value in the IPL[2:0] field. If the values are the same, then a chip-select can be asserted,
provided other option register conditions are met. When the SPACE[1:0] field has any value except
%00, the IPL[2:0] field determines whether an access takes place in program or data space. Table 30
shows IPL[2:0] field encoding.
1. The CPU16 executes code only in supervisor
mode, therefore this space field encoding has
no effect. Supervisor/User space is equivalent
to supervisor space encoding.
Table 28 DSACK Field Encoding
DSACK[3:0]
Clock Cycles Required
Per Access
Wait States Inserted
Per Access
0000
3
0
0001
4
1
0010
5
2
0011
6
3
0100
7
4
0101
8
5
0110
9
6
0111
10
7
1000
11
8
1001
12
9
1010
13
10
1011
14
11
1100
15
12
1101
16
13
1110
2
1 (Fast Termination)
1111
—
External DSACK
Table 29 Address Space Bit Encodings
SPACE[1:0]
Address Space
00
CPU Space
01
User Space1
10
Supervisor Space
11
Supervisor/User Space1
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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