參數(shù)資料
型號： MC68HC916X1CTH16
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
封裝： QFP-120
文件頁數(shù)： 115/172頁
文件大?。?/td> 1200K
代理商： MC68HC916X1CTH16
MC68HC916X1
MOTOROLA
MC68HC916X1TS/D
47
The bits in this register control the direction of the pin drivers when the pins are configured as I/O.
Any bit in this register set to one configures the corresponding pin as an output. Any bit in this reg-
ister cleared to zero configures the corresponding pin as an input. This register can be read or writ-
ten at any time the MCU is not in emulator mode.
The bits in PEPAR control the function of each port E pin. Any bit set to one defines the correspond-
ing pin to be a bus control signal, with the function shown in Table 32. Any bit cleared to zero de-
fines the corresponding pin to be an I/O pin, controlled by PORTE and DDRE.
BERR and DATA8 control the state of this register following reset. If BERR and/or DATA8 are low
during reset, this register is set to $00, defining all port E pins as I/O pins. If BERR and DATA8 are
both high during reset, the register is set to $FF, which defines all port E pins as bus control signals.
3.10.3 Port F
Port F pins can be configured as interrupt request inputs, edge-detect input/outputs, or discrete in-
put/outputs. When port F pins are configured for edge detection, and a priority level is specified by
writing a value to the port F edge-detect interrupt level register (PFLVR), port F control logic gener-
ates an interrupt request when the specified edge is detected. Interrupt vector assignment is made
by writing a value to the port F edge-detect interrupt vector register (PFIVR). The edge-detect inter-
rupt has the lowest arbitration priority in the SCIM.
A write to the port F data register is stored in the internal data latch, and if any port F pin is config-
ured as an output, the value stored for that bit is driven on the pin. A read of PORTF returns the
value on a pin only if the pin is configured as a discrete input. Otherwise, the value read is the value
stored in the data register.
1. Reserved
PEPAR — Port E Pin Assignment
$YFFA17
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PEPA7 PEPA6 PEPA5 PEPA4 RESERVED PEPA1 RSVD1
RESET:
8- AND 16-BIT EXPANDED MODES
DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8
SINGLE-CHIP MODE
0
Table 32 Port E Pin Assignments
PEPAR Bit
Port E Signal
Bus Control Signal
PEPA7
PE7
SIZ1
PEPA6
PE6
SIZ0
PEPA5
PE5
AS
PEPA4
PE4
DS
PEPA1
PE1
DSACK1
PORTF0, PORTF1 — Port F Data Register
$YFFA19, YFFA1B
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
PF7
PF6
RESERVED
PF0
RESET:
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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