參數(shù)資料
型號： MC68HC05G3
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁數(shù)： 96/128頁
文件大?。?/td> 290K
代理商： MC68HC05G3
Page vii
MOTOROLA
MC68HC05G3 (705G4) Specification Rev. 1.1
LIST OF FIGURES
Figure 1-1:
Block Diagram of the MC68HC05G3 (705G4)..........................................2
Figure 1-2:
Pin Assignment for Single-Chip Mode ......................................................3
Figure 1-3:
Memory Map of MC68HC05G3 ................................................................4
Figure 1-4:
Memory Map of MC68HC705G4 ..............................................................5
Figure 1-5:
Clock Signal Distribution ...........................................................................6
Figure 1-6:
OSC1/2 and XOSC1/2 Mask Options .......................................................7
Figure 1-7:
Clock State and STOP/POD Delay Diagram ..........................................10
Figure 1-8:
Time Base Clock Divider ........................................................................11
Figure 1-9:
Register Description Key ........................................................................17
Figure 1-10:
Main I/O Map ($0000-$000F) .................................................................18
Figure 1-11:
Main I/O Map ($0010-$001F) .................................................................19
Figure 1-12:
Main I/O Map ($0034-$003F) .................................................................20
Figure 1-13:
Option Map ($0000-$000F) ....................................................................21
Figure 2-1:
HC05G3 (705G4) Mode Entry Diagram..................................................28
Figure 3-1:
MC68HC05G3 (705G4) Memory Map ....................................................30
Figure 4-1:
Programming Model ...............................................................................33
Figure 4-2:
Stacking Order ........................................................................................34
Figure 4-3:
STOP/WAIT Flowcharts..........................................................................43
Figure 5-1:
Interrupt Flowchart ..................................................................................47
Figure 5-2:
IRQ1 and IRQ2 Block Diagram...............................................................48
Figure 5-3:
Key Wakeup Interrupt (KWI) ...................................................................49
Figure 6-1:
Port I/O Circuitry for One Bit ...................................................................57
Figure 7-1:
SPI Master-Slave Interconnection ..........................................................70
Figure 7-2:
SPI Block Diagram..................................................................................70
Figure 7-3:
Clock-Data Timing Diagram....................................................................72
Figure 8-1:
Timer Block Diagram ..............................................................................81
Figure 8-2:
Timer 1 Block Diagram ...........................................................................82
Figure 8-3:
Timer 2 Block Diagram ...........................................................................88
相關(guān)PDF資料
PDF描述
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