參數(shù)資料
型號: MC68HC05G3
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 38/128頁
文件大?。?/td> 290K
代理商: MC68HC05G3
Page 7
Section 1: INTRODUCTION
MOTOROLA
MC68HC05G3 (705G4) Specification Rev. 1.1
1.4.1.2
XOSC ON LINE
The secondary oscillator (XOSC) runs continuously after power-up.
If XOSC is the system clock (SYS0:1=1:1), OSC can be stopped either by the STOP
instruction or by clearing the FOSCE bit.
The sub oscillator (XOSC) never stops except during power down. This clock also may be
used as the source for the system clock and/or time base.
OSC and XOSC pins have options for feedback and damping resistor implementations.
These options are set through mask option and may be read through the MOSR register.
Figure 1-6: OSC1/2 and XOSC1/2 Mask Options
XOSC WITH FOSCE=1
If XOSC is the system clock and FOSCE=1, executing the STOP instruction will halt OSC,
put the MCU into a low-power mode and clear the 6-bit POD counter. The 7-bit divider is
not initialized. Exiting STOP with external IRQ re-starts the oscillator; however, execution
begins immediately using XOSC. When the POD counter overflows, FTUP is set signaling
that OSC is stable and OSC can be used as the system clock. The stabilization time will
vary between 8064 and 8192 counts.
XOSC WITH FOSCE=0
If XOSC is the system clock, clearing FOSCE will stop OSC and preset the 7-bit divider plus
the 6-bit POD counter to $0078. Execution will continue with XOSC, and when FOSCE is
set again, OSC will re-start. When the POD counter overflows, FTUP is set signaling that
OSC is stable and OSC can be used as the system clock. The stabilization time will be 8072
counts.
Rf
Rd
XOSC1
XOSC2
XOSC
OSC1
OSC2
OSC
MASK
OPTION
MASK
OPTION
ON CHIP
OFF CHIP
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