參數(shù)資料
型號: MC68HC05G3
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 25/128頁
文件大小: 290K
代理商: MC68HC05G3
Page 110
MOTOROLA
Section 10: A/D CONVERTER
MC68HC05G3 (705G4) Specification Rev. 1.1
10.5
A/D DATA REGISTER ($3A)
One 8-bit result register is provided. This register is updated each time COCO is set.
Figure 10-2: A/D Data Register
10.6
A/D DURING WAIT MODE
The A/D continues normal operation during wait mode. To decrease power consumption
during WAIT, it is recommended that both the ADON and ADRC bits in the A/D status and
control register be cleared if the A/D converter is not being used. If the A/D converter is in
use and the system clock rate is above 1.0 MHz, it is recommended that the ADRC bit be
cleared.
10.7
A/D DURING STOP MODE
In stop mode the comparator and charge pump are turned off and the A/D ceases to
function. Any pending conversion is aborted. When the clocks begin oscillation upon
leaving the stop mode, a finite amount of time passes before the A/D circuits stabilize
enough to provide conversions to the specified accuracy. Normally, the delays built into the
MC68HC05G3 when coming out of stop mode are sufficient for this purpose. Therefore, no
explicit delays need to be built into the software.
$003A
ADR
B7
B6
B5
B4
B3
B2
B1
B0
UUUUUUUU
RESET:
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