參數(shù)資料
型號: MC68HC05G3
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 16/128頁
文件大?。?/td> 290K
代理商: MC68HC05G3
Page 102
MOTOROLA
Section 9: PULSE WIDTH MODULATOR
MC68HC05G3 (705G4) Specification Rev. 1.1
This results in a monotonic change of the DC component of the output without overshoots
or vicious starts. (A vicious start is an output which gives totally erroneous PWM during the
initial period following an update of the PWM register.) This feature is achieved by double
buffering of the PWM registers.
All PWM duty registers are reset to $00 during power-on or external reset.
9.4
PWM COUNTER (PWMCNT)
The PWM counter may be read any time without affecting the count or the operation of the
PWM channel. The PWM counter (PWMCNT) is incremented by the falling edge of the
PWM timer clock (which is synchronized and has the same timing as the falling edge of
PHI2).
The PWMCNT register is initialized to $01 if it overflows. However, this counter is initialized
to $FF when this register is written by the CPU or all channels are disabled. Writes to the
counter while the channel(s) is enabled (counting) may cause a truncated PWM period.
When the channel(s) is enabled (CH
x written from zero to one), the PWM counter starts
incrementing using whichever clock it has selected.
9.5
PWM DURING WAIT MODE
The PWM continues normal operation during wait mode. To decrease power consumption
during WAIT, it is recommended that the CH3-0 bits in the PWMCR register be cleared if
the PWM is not being used.
9.6
PWM DURING STOP MODE
In stop mode the system clock is stopped causing the PWM to cease function. Any signal
in process is suspended in whatever phase the signal happens to be in. When the clock
begins oscillation upon leaving stop mode, the PWM will resume where it left off.
$00
$01
$80
$FF
T
128T
127T
254T
255T
Figure 9-4: PWM Waveform Examples (E = 2MHz; CLK = E/2)
1/255T = 3921 Hz, and T = 1/(255X3921)
1.0 S, so T = 2 CPU clocks
Figure 9-5: PWM Counter
$0035
PWMCNT
B7
B6
B5
B4
B3
B2
B1
B0
11111111
RESET:
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