參數(shù)資料
型號: MC68HC05G3
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 43/128頁
文件大?。?/td> 290K
代理商: MC68HC05G3
Page 11
Section 1: INTRODUCTION
MOTOROLA
MC68HC05G3 (705G4) Specification Rev. 1.1
1.4.1.6
TIME BASE
Time base is a 14-bit up counter which is clocked by XOSC input or OSC input divided by
128. The TBCLK bit in the TBCR1 register selects the clock source.
This divider is initialized to $0078 only on power-on delay. After counting 8072 clocks,
STUP bit in the MISC register is set.
Figure 1-8: Time Base Clock Divider
The divided clocks from the time base are used as follows:
STUP
Time base divider is initialized to $0078 by the power-on detection. When the
count reaches 8072, the STUP flag in the MISC register is set. Once STUP
flag is set, it is never cleared until power down.
TBI
Time base interrupt may be generated at every 0.5, 0.25, 0.125, or 0.0039
seconds with 32.768 KHz crystal at XOSC pins.
Time base interrupt flag (TBIF) is set at every period and interrupt is
requested if the enable bit (TBIE) is set. The clock divided by 128, 4096,
8192, or 16,384 is used to set TBIF, and this clock is selected by the TBR1
and TBRO bits in the TBCR2 register.
S
E
L
S
E
L
7-BIT DIVIDER
DIVIDED BY 4
TBIF
1/20
1/25
1/26
1/27
OSC/27
XCLK
TBCLK
TBI
COP RESET
TBR0
COP
CLEAR
COP
ENABLE
TBR1
TBIE
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