參數(shù)資料
型號: MC68HC05G3
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 124/128頁
文件大?。?/td> 290K
代理商: MC68HC05G3
Page 85
Section 8: TIMER SYSTEM
MOTOROLA
MC68HC05G3 (705G4) Specification Rev. 1.1
The comparison between the counter and the OC2 buffer register is done while the system
clock is high in each bus cycle. If the counter matches with the OC2 buffer register, the
comparator latches this result during the current timer cycle. When the next timer cycle
begins, the comparator outputs CMP2 signal (if the compare match is detected during the
previous timer cycle). This CMP2 is used in the counter preset, data transfer to the buffer
register, setting OC2F in the TSR2, and the EVO block. The counter preset overrides the
counter increment.
The OC2F bit may generate interrupt request if the OC2IE bit in the TCR2 is set to 1.
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