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參數(shù)資料
| 型號： | MC68HC05G3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 123/128頁 |
| 文件大?。?/td> | 290K |
| 代理商： | MC68HC05G3 |
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Page 84
MOTOROLA
Section 8: TIMER SYSTEM
MC68HC05G3 (705G4) Specification Rev. 1.1
8.2
TIMER 2
Timer 2 is an 8-bit event counter which has one compare register, event input pin (EVI),
and event output pin (EVO). The event counter is clocked by the external clock (EXCLK)
or prescaled system clock (CLK2) that is selected by the T2CLK bit in the TCR2 register.
The EXCLK may be EVI direct or EVI gated by CLK2, which is selected by the IM2 bit at
the EVI block. (Refer to the EVI description.)
Timer 2 may be used as a modulus clock divider with EVO pin, free-running counter (when
compare register is $00), or periodic interrupt timer.
The timer counter 2 is an 8-bit up counter with preset input. The counter is preset to $01 by
the CMP2 signal from the comparator or a CPU write to this counter (TCNT2), done while
the system clock (PHI2) is low.
The CLK2 from the prescaler or the EXTCLK from the EVI block are selected as timer clock
by the T2CLK bit in the TCR2 register. The CLK2 and the EXCLK are synchronized to the
falling edge of system clock in the prescaler and the EVI blocks. The minimum pulse width
of CLK2 is the same as the system clock, and the minimum pulse width of EXCLK (event
mode) is one PHI2 cycle. When the EXCLK (event mode) is selected, 50% duty is not
guaranteed.
Figure 8-3: Timer 2 Block Diagram
The counter is incremented by the falling edge of the timer clock and the period between
two falling edges is defined as one timer cycle in the following description.
The compare register (OC2) is provided for the comparison with the timer counter. The
OC2 data is transferred to the buffer register when the counter is preset by the CPU write
or the compare output (CMP2). Actually, this buffer register is compared with the timer
counter.
COUNTER 2
COMPARATOR 2
REGISTER (OC2)
BUFFER 2
S
E
L
(TRANSFER)
($01)
0
1
COUNTER
WRITE
CLK2
EXCLK
T2CLK
CMP2
TIMCLK
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