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參數(shù)資料
| 型號： | MC68HC05G3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 14/128頁 |
| 文件大?。?/td> | 290K |
| 代理商： | MC68HC05G3 |
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Page 100
MOTOROLA
Section 9: PULSE WIDTH MODULATOR
MC68HC05G3 (705G4) Specification Rev. 1.1
or TIMCLK is divided by any positive integer up to 256 when CMP2 is selected. Obviously,
CMP2 should be selected only if timer 2 is not being used or if it is generating a desired
frequency that could be shared. Refer to 8.2 Timer 2 for more information on using CMP2.
The following table shows the PWM clock selections.
Table 9-1: PWM Clock Selection
NOTE:
While bits T3R1 and T3R0 may be written any time, if the selection is
changed while a PWM signal is being generated, a truncated or stretched
pulse may occur during the transition. To prevent this from happening, it
is recommended that all PWM channels be disabled or the counter be
forced to $FF when changing clock selections.
CLK3 from the prescaler is activated by enabling the PWM channel(s). This is done to
ensure that the moment the first PWM channel(s) is enabled, the counter can start
incrementing without any clock delays. This does not apply to CMP2, since CMP2 is
controlled by timer 2.
The counter is incremented by the falling edge of the timer clock and is either preset to $01
by the overflow (OVF) from the counter, $FF by disabling all PWM channels, or writing to
this counter (PWMCNT) while the system clock (PHI2) is low.
Since only one counter is shared by all the channels, only the first PWM signal output(s)
can be synchronized to the starting edge of the CLK3 clock when the channel(s) is enabled.
This first PWM signal output(s) will initiate with a complete PWM period.
Any channel
enabled after the starting edge of the CLK3 clock will generate a truncated pulse during the
initial period.
Each channel has its own 8-bit duty register which is double buffered. When a channel is
active (enable bit is high), writes to the duty register are buffered until the counter rolls over.
At this time the new duty takes effect. In this way, the output of the PWM always will be
either the old duty waveform or the new duty waveform, not some variation in between.
A change in duty can be forced into effect immediately by writing the new value to the duty
register and then writing any value to the counter. This causes the counter to reset to $FF
and the newly latched duty value to be transferred to the buffer. In addition, since the
counter is readable, it is possible to know where the count is with respect to the duty value
and software can be used to make the adjustments.
T3R1
T3R0
0
1
0
1
0
1
E
E/2
E/8
TIMCLK*/N (N=1....256)
PWM CLOCK
(CLK3)
(CMP2)
* TIMCLK = CLK2 or EXCLK
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