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| 型號(hào)： | MC68HC05G3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁(yè)數(shù)： | 106/128頁(yè) |
| 文件大小： | 290K |
| 代理商： | MC68HC05G3 |
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Page 69
Section 7: SERIAL PERIPHERAL INTERFACE (SPI)
MOTOROLA
MC68HC05G3 (705G4) Specification Rev. 1.1
7.3.2
SERIAL CLOCK (SCK)
The serial clock (SCK) is used for synchronization of both the input and output data streams
through its SDI and SDO pins. PC3(SCK) should be high before the SPI is enabled. This
can be done with the internal resistor or an external resistor, or by setting DDRC3=1 and
PC3=1.
The master and slave devices are capable of exchanging a data byte during a sequence of
eight clock pulses. Since the SCK is generated by the master/slave, data transfer is
accomplished by synchronization to SCK.
The master generates the SCK through a circuit driven by the internal processor clock, and
uses the SCK to latch incoming slave device data on the SDI pin and to shift out data to the
slave via the SDO pin. The SPR bit in the SPCR of the master selects the clock rate.
The slave device receives the SCK from the master device and uses the SCK to latch
incoming master device data on the SDI pin and to shift out data to the master via the SDO
pin. The SPR bit in the SPCR of the slave has no meaning.
7.4
REGISTERS
Three registers in each serial peripheral interface (SPI) provide control, status, and data
storage functions. These three registers are the serial peripheral control register (SPCR
location $000A/$000D), serial peripheral status register (SPSR location $000B/$000E),
and serial peripheral data register (SPDR location $000C/$000F).
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相關(guān)代理商/技術(shù)參數(shù) |
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