參數(shù)資料
型號(hào): MC68HC05G3
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁(yè)數(shù): 113/128頁(yè)
文件大?。?/td> 290K
代理商: MC68HC05G3
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Page 75
Section 7: SERIAL PERIPHERAL INTERFACE (SPI)
MOTOROLA
MC68HC05G3 (705G4) Specification Rev. 1.1
7.5
PORT FUNCTION
SPI1 module shares the port with PC0 through PC2 and SPI2 module shares the port with
PG0 through PG2.
The SPI1 shares I/O pins with PC0 through PC2. When SPE1 is set, PC0 becomes SDI1
input, PC1 becomes SDO1 output and PC2 becomes SCK1. The direction of SCK1
depends on MSTR1 bit. Setting DDRC bits 0-2 does not change the data direction of the
pin to output, but instead changes the source of data when PC0-2 is read. If DDRC
x = 1,
port C bit-
x data latch is read and if DDRCx = 0, PORTCx pin level is read by the CPU.
The SPI2 shares I/O pins with PG0 through PG2. When SPE2 is set, PG0 becomes SDI2
input, PG1 becomes SDO2 output and PG2 becomes SCK2. The direction of SCK2
depends on MSTR2 bit. Setting DDRG bits 0-2 does not change the data direction of the
pin to output, but instead changes the source of data when PG0-2 is read. If DDRG
x = 1,
port G bit-
x data latch is read and if DDRGx = 0, PORTGx pin level is read by the CPU.
When SPE
x is cleared, SPIx is disconnected and PC0 through PC2 (SPI1) or PG0 through
PG2 (SPI2) are used as general-purpose I/O pins. For more information on the ports, see
6.3 PORT C, and 6.7 PORT G.
相關(guān)PDF資料
PDF描述
MC68HC705J5ACJP 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP16
MC68HC705J5ACP 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP20
MC68HC05J5AJDW 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO16
MC68HRC705J5ACDW 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO20
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