參數(shù)資料
型號： MC68HC05G3
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁數(shù)： 119/128頁
文件大?。?/td> 290K
代理商： MC68HC05G3
Page 80
MOTOROLA
Section 8: TIMER SYSTEM
MC68HC05G3 (705G4) Specification Rev. 1.1
Because neither the output compare flag (OCF bit) nor output compare register is affected
by reset, care must be exercised when initializing the output compare function with
software. The following procedure is recommended:
1. Set DDRG3 bit to configure PG3 as an output tied to TCMP.
2. Write to the high byte of the output compare register to inhibit further
compares until the low byte is written.
3. Read the timer status register to arm the OCF if it is already set.
4. Write to the low byte of the output compare register to enable the output
compare function with the flag clear.
The advantage of this procedure is to prevent the OCF bit from being set between the time
it is read and the write to the output compare register. A software example is shown below.
10
3E
BSET OPTM,MISC
SWITCH TO OPTION MAP
16
06
BSET DDRG3,DDRG
CONFIGURE PG3 AN OUTPUT
11
3E
BCLR OPTM,MISC
RETURN TO MAIN MAP
B7
16
STA OCMPHI
INHIBIT OUTPUT COMPARE
B6
13
LDA TSTAT
ARM OCF BIT IF SET
BF
17
STX OCMPLD
READY FOR NEXT COMPARE
8.1.3
INPUT CAPTURE REGISTER
Two 8-bit registers, which make up the 16-bit input capture register, are read-only and are
used to latch the value of the free-running counter after the corresponding input capture
edge detector senses a defined transition. The level transition which triggers the counter
transfer is defined by the corresponding input edge bit (IEDG). Reset does not affect the
contents of the input capture register.
The result obtained by an input capture will be one more than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition. This
delay is required for internal synchronization. Resolution is one count of the free-running
counter, which is four internal bus clock cycles.
The free-running counter contents are transferred to the input capture register on each
proper signal transition regardless of whether the input capture flag (ICF) is set or clear.
The input capture register always contains the free-running counter value that corresponds
to the most recent input capture.
After a read of the input capture register ($14) MSB, the counter transfer is inhibited until
the LSB ($15) also is read. This characteristic causes the time used in the input capture
software routine and its interaction with the main program to determine the minimum pulse
period.
A read of the input capture register LSB ($15) does not inhibit the free-running counter
transfer since they occur on opposite edges of the internal bus clock.
相關(guān)PDF資料
PDF描述
MC68HC705J5ACJP 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP16
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參數(shù)描述
MC68HC05J1 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS MICROCONTROLLER UNIT
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MC68HC05J1ACDW 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers
MC68HC05J1ACP 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers
MC68HC05J1ADW 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers
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