參數(shù)資料
型號(hào)： MC68HC05G3
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁數(shù)： 92/128頁
文件大?。?/td> 290K
代理商： MC68HC05G3
Page 56
MOTOROLA
Section 6: INPUT/OUTPUT PORTS
MC68HC05G3 (705G4) Specification Rev. 1.1
6.3
PORT C
Port C pins share functions with several on-chip peripherals. A pin function is controlled by
the enable bit of each associated peripheral.
PC7 and PC6 are general-purpose I/O pins and IRQ input pins. The DDRC7/6 bits
determine whether the pin states or data latch states should be read by the CPU. When
DDRC7/6 =1, the pins become open drain outputs and the IRQ
xF can be set by the data
latch. Therefore, be sure to clear the flag by software before the IRQ
xE bit is enabled.
The PC5 pin is a general-purpose I/O pin and the direction of the pin is determined by the
DDRC5 bit in data direction register C (DDRC). When the event output (EVO) is enabled,
PC5 is configured as an event output pin and the DDRC5 bit has meaning only for the read
of PC5 bit in the PORTC register. If the DDRC5 is set, the PC5 data latch is read by the
CPU; otherwise, the PC5 pin level (EVO state) is read. When EVO is disabled, the DDRC5
bit decides the idling state of EVO (if DDRC5 = 1). This PC5/EVO output has the capability
to drive a 10 mA source current when (Voh
≥ V
DD - 0.8 V).
The PC4 and PC3 pins share functions with the timer input pins (EVI and TCAP). These
bits are not affected by the usage of timer input functions, and the directions of pins are
always controlled by the DDRC4 and DDRC3 bits. Also, the DDRC4 and DDRC3 bits
determine whether the pin states or data latch states should be read by the CPU.
The PC2 through PC0 pins are shared with the serial peripheral interface (SPI1). When the
SPI1 is not used (SPE1 = 0), DDRC2 through DDRC0 bits control the directions of the pins,
and when the SPI1 is enabled, the pins are configured as serial clock output or input
(SCK1), serial data output (SDO1), and serial data input (SDI1). The direction of the SCK1
depends on the MSTR1 bit in the SPCR1. The DDRC2 through DDRC0 bits always affect
the CPU read of PORTC register (pin states for the input configuration or data latch for the
output configuration).
Each port C pin has a pullup resistor option controlled by the corresponding RCR2 register
bit. (The typical resistor values are to be 10 K
@ 3 V.) When a pin outputs low, the resistor
is disconnected regardless of an RCR2 register bit being set.
Bit 5 through bit 0 have open drain or CMOS output options, which are controlled by the
corresponding WOM2 register bits. Bits 7 and 6 have fixed open drain outputs. These open
drain or CMOS output options are effective to either the general-purpose outputs or the
peripheral outputs (EVO, SCK1, and SDO1).
相關(guān)PDF資料
PDF描述
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