- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67967 > MC68HC05G3 (MOTOROLA INC) 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80 PDF資料下載
參數(shù)資料
| 型號(hào)： | MC68HC05G3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁(yè)數(shù)： | 92/128頁(yè) |
| 文件大小： | 290K |
| 代理商： | MC68HC05G3 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)當(dāng)前第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)
Page 56
MOTOROLA
Section 6: INPUT/OUTPUT PORTS
MC68HC05G3 (705G4) Specification Rev. 1.1
6.3
PORT C
Port C pins share functions with several on-chip peripherals. A pin function is controlled by
the enable bit of each associated peripheral.
PC7 and PC6 are general-purpose I/O pins and IRQ input pins. The DDRC7/6 bits
determine whether the pin states or data latch states should be read by the CPU. When
DDRC7/6 =1, the pins become open drain outputs and the IRQ
xF can be set by the data
latch. Therefore, be sure to clear the flag by software before the IRQ
xE bit is enabled.
The PC5 pin is a general-purpose I/O pin and the direction of the pin is determined by the
DDRC5 bit in data direction register C (DDRC). When the event output (EVO) is enabled,
PC5 is configured as an event output pin and the DDRC5 bit has meaning only for the read
of PC5 bit in the PORTC register. If the DDRC5 is set, the PC5 data latch is read by the
CPU; otherwise, the PC5 pin level (EVO state) is read. When EVO is disabled, the DDRC5
bit decides the idling state of EVO (if DDRC5 = 1). This PC5/EVO output has the capability
to drive a 10 mA source current when (Voh
≥ V
DD - 0.8 V).
The PC4 and PC3 pins share functions with the timer input pins (EVI and TCAP). These
bits are not affected by the usage of timer input functions, and the directions of pins are
always controlled by the DDRC4 and DDRC3 bits. Also, the DDRC4 and DDRC3 bits
determine whether the pin states or data latch states should be read by the CPU.
The PC2 through PC0 pins are shared with the serial peripheral interface (SPI1). When the
SPI1 is not used (SPE1 = 0), DDRC2 through DDRC0 bits control the directions of the pins,
and when the SPI1 is enabled, the pins are configured as serial clock output or input
(SCK1), serial data output (SDO1), and serial data input (SDI1). The direction of the SCK1
depends on the MSTR1 bit in the SPCR1. The DDRC2 through DDRC0 bits always affect
the CPU read of PORTC register (pin states for the input configuration or data latch for the
output configuration).
Each port C pin has a pullup resistor option controlled by the corresponding RCR2 register
bit. (The typical resistor values are to be 10 K
@ 3 V.) When a pin outputs low, the resistor
is disconnected regardless of an RCR2 register bit being set.
Bit 5 through bit 0 have open drain or CMOS output options, which are controlled by the
corresponding WOM2 register bits. Bits 7 and 6 have fixed open drain outputs. These open
drain or CMOS output options are effective to either the general-purpose outputs or the
peripheral outputs (EVO, SCK1, and SDO1).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC705J5ACJP | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP16 |
| MC68HC705J5ACP | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP20 |
| MC68HC05J5AJDW | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO16 |
| MC68HRC705J5ACDW | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
| MC68HRC05J5ADW | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05J1 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC05J1A | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC68HC05J1ACDW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC68HC05J1ACP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC68HC05J1ADW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。