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參數(shù)資料
| 型號： | MC68HC05G3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 68/128頁 |
| 文件大?。?/td> | 290K |
| 代理商： | MC68HC05G3 |
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Page 34
MOTOROLA
Section 4: CPU CORE
MC68HC05G3 (705G4) Specification Rev. 1.1
4.1.4
STACK POINTER (SP)
The stack pointer contains the address of the next free location on the stack. During an
MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location
$00FF. The stack pointer then is decremented as data is pushed onto the stack and
incremented as data is pulled from the stack.
When accessing memory, the 10 most significant bits are permanently set to 0000000011.
These 10 bits are appended to the six least significant bits to produce an address within the
range of $00FF to $00C0. Subroutines and interrupts may use up to 64 (decimal) locations.
If 64 locations are exceeded, the stack pointer wraps around and loses the previously
stored information. A subroutine call occupies two locations on the stack; an interrupt uses
five locations. See Figure 4-2: Stacking Order.
Figure 4-2: Stacking Order
NOTE:
Since the stack pointer decrements during pushes, the PCL is stacked
first, followed by PCH, etc. Pulling from the stack is in the reverse order.
4.1.5
CONDITION CODE REGISTER (CCR)
The CCR is a 5-bit register in which four bits are used to indicate the results of the
instruction just executed, and the fifth bit indicates whether interrupts are masked. These
bits can be tested individually by a program, and specific actions can be taken as a result
of their state. Each bit is explained in the following paragraphs.
4.1.6
HALF CARRY (H)
This bit is set during ADD and ADC operations to indicate that a carry occurred between
bits 3 and 4.
4.1.6.1
INTERRUPT (I)
When this bit is set, the timer and external interrupt are masked (disabled). If an interrupt
occurs while this bit is set, the interrupt is latched and processed as soon as the interrupt
bit is cleared.
Index Register
PCL
Accumulator
Condition Code Register
PCH
11
1
70
Stack
I
N
T
E
R
U
P
T
Decreasing
Unstack
R
E
T
U
R
N
Increasing
Memory
Addresses
Memory
Addresses
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