參數(shù)資料
型號: MC68HC05G3
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 46/128頁
文件大小: 290K
代理商: MC68HC05G3
Page 14
MOTOROLA
Section 1: INTRODUCTION
MC68HC05G3 (705G4) Specification Rev. 1.1
TBIF
Time Base Interrupt Flag
The TBIF bit is set every timeout interval of the time base. This is a read-only bit
and is cleared by writing a one to the RTBIF bit. Reset clears the TBIF bit. Time
base interrupt period between reset and first TBIF depends on the time elapsed
during reset, since the time base divider is not initialized by reset.
TBIE
Time Base Interrupt Enable
The TBIE bit enables the time base interrupt capability. If TBIF = 1 and TBIE =
1, the time base interrupt is generated.
0 - TB interrupt is disabled
1 - TB interrupt requested when TBIF = 1
TBR1/0
Time Base Interrupt Rate Select
The TBR1 and TBR0 bits select one of four rates for the time base interrupt
period. The TB interrupt rate is also related to the COP reset period. These bits
are set to one by reset.
RTBIF
Reset TB Interrupt Flag
The RTBIF bit is a write-only bit and always read as zero. Writing a one to this
bit clears the TBIF bit and writing zero to this bit has no effect.
BIT 2
Reserved
This bit is not used and always read as zero.
COPE
COP Enable
When the COPE bit is 1, COP reset function is enabled. This bit is cleared by the
reset (including COP reset) and write to this bit is allowed only one time after
reset.
COPC
COP Clear
Writing a one to COPC bit clears the 2-bit divider to prevent COP timeout. (The
COP timeout period depends on the TB interrupt rate.) This bit is write-only and
returns to zero when read.
TBR1
TBR0
DIVIDE RATIO
FREQUENCY (HZ)
OSC=
4.0M
OSC=
4.1943M
XOSC=
32.768K
0
1
0
1
0
1
TBCLK DIVIDED BY 128
TBCLK DIVIDED BY 4096
TBCLK DIVIDED BY 8192
TBCLK DIVIDED BY 16,384
244
7.63
3.81
1.91
256
8.00
4.00
2.00
256
8.00
4.00
2.00
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