參數資料
型號: MC68HC05G3
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數: 4/128頁
文件大?。?/td> 290K
代理商: MC68HC05G3
Page 91
Section 8: TIMER SYSTEM
MOTOROLA
MC68HC05G3 (705G4) Specification Rev. 1.1
8.4.3
TIMER OUTPUT 1 (TCMP)
This output pin is used for the output compare of timer 1. Active output level (high or low
level) is selected by the OLVL bit in the TCR.
8.4.4
TIMER OUTPUT 2 (EVO)
The EVO pin is the clock output pin of timer 2. The compare output from the timer 2 (CMP2)
is divided in this block for 50% duty output signal. This 1/2 divider is initialized to the level
of the OL2 bit when the timer counter 2 is written by the CPU (initialized).
Figure 8-9: EVO Block Diagram
When the OE2 bit in the timer control register 2 (TCR2) is set, the EVO output is activated
and when OE2 is cleared EVO is deactivated.
The output buffer at the EVO/PC5 pin is enabled when the DDRC5 bit is set or the
synchronized output enable is high (clock on). If DDRC5 bit is set to one, the pin state
during the idling condition (clock off) is decided by the PC5 data latch. If DDRC5 is cleared,
the pin becomes high impedance during clock off.
1/2
D
C
Q
SEL
PC5
EVO
OE2
OL2
CMP2
CNTR2
WRITE
PC5 (Out)
PC5 (In)
DDRC5
1
0
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