參數(shù)資料
型號(hào): MC68HC05G3
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 80/128頁
文件大?。?/td> 290K
代理商: MC68HC05G3
Page 45
Section 5: RESET/ INTERRUPT STRUCTURE
MOTOROLA
MC68HC05G3 (705G4) Specification Rev. 1.1
SECTION 5
RESET/ INTERRUPT STRUCTURE
5.1
GENERAL
In user operating modes, the reset/interrupt vectors are located at the top of the address
space ($FFF0 through $FFFF). In the self-check (bootstrap) mode, the reset/interrupt
vectors are located at $FFE0 through $FFEF in the internal self-check (bootstrap) ROM.
For the remainder of this section, a user operating mode will be assumed. The following
table shows the address assignments for the vectors.
Table 5-1: Interrupt Vector Assignments
Upon reset, the I bit in the condition code register is set and no interrupts are recognized.
Also, when an interrupt occurs, the I bit automatically is set by hardware after stacking the
CC byte. All interrupts in the MC68HC05G3 (705G4) follow a fixed hardware priority circuit
to resolve simultaneous requests. Each of these sources is an input to the priority
resolution circuit.
Each interrupt has a software programmable interrupt mask bit which may be used to
selectively inhibit automatic hardware response. In addition, the I bits in the condition code
register act as class inhibit masks to inhibit all sources in the I bit class. The RESET and
software interrupt (SWI) are not masked by the I bit in the condition code register.
VECTOR
MASKED
LOCAL
PRIORITY
ADDRESS
INTERRUPT SOURCE
BY
MASK
(1 = HIGHEST)
FFF0-F1
TBI
I BIT
TBIE
7
FFF2-F3
SPI
SPI1
I BIT
SPIE1
6
SPI2
I BIT
SPIE2
6
FFF4-F5
TIMER 2
TI2I
I BIT
TI2IE
5
OC2I
I BIT
OC2IE
5
FFF6-F7
TIMER 1
ICI
I BIT
ICIE
4
OC1I
I BIT
OC1IE
4
TOI
I BIT
TOIE
4
FFF8-F9
KWI
I BIT
KWIE
3
FFFA-FB
IRQ
IRQ1
I BIT
IRQ1E
2
IRQ2
I BIT
IRQ2E
2
FFFC-FD
SWI
NONE
*
FFFE-FF
RESET
COP
NONE
COPE
1
RESET PIN
NONE
1
* Same level as an instruction
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