參數(shù)資料
型號(hào)： MC68HC05G3
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁數(shù)： 7/128頁
文件大小： 290K
代理商： MC68HC05G3
Page 94
MOTOROLA
Section 8: TIMER SYSTEM
MC68HC05G3 (705G4) Specification Rev. 1.1
IL2
Timer Input 2 active edge (Level) select
The IL2 bit selects the active edge of EVI to increment counter for the event
mode (IM2 = 0), or gate enable level of EVI for the gate mode (IM2 = 1). This bit
is cleared at reset.
0 - Falling edge is selected (event mode)
Low level enables counting (gate mode)
1 - Rising edge is selected (event mode)
High level enables counting (gated mode)
OE2
Timer Output 2 (EVO) Output Enable
The OE2 bit enables EVO output on PC5 pin. When this bit is changed, the
control of the pin is delayed (synchronized) until the next active edge of EVO is
selected by OL2 bit occurs. This bit is cleared at reset.
0 - EVO output is disabled
1 - EVO output is enabled
OL2
Timer Output 2 Edge select for synchronization
The OL2 bit selects which edge of EVO clock should be synchronized by the OE2
bit control. The OL2 bit also decides the initial value of the CMP2 divider, when
counter 2 is written by the CPU. This bit is cleared at reset.
0 - The falling edge of EVO switches EVO output and PC5 if the OE2 bit has
been
changed.
1 - The rising edge of EVO switches EVO output and PC5 if the OE2 bit has
been changed.
IM2
IL2
Action on Clock
0
EVI Falling Edge Increments Counter
0
1
EVI Rising Edge Increments Counter
1
0
Low Level on EVI Enables Counting
1
High Level on EVI Enables Counting
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PDF描述
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