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參數(shù)資料
| 型號： | MC68HC05BS8FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 81/128頁 |
| 文件大?。?/td> | 752K |
| 代理商： | MC68HC05BS8FB |
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MOTOROLA
6-12
MC68HC05BS8
TIMERS
6
RTIF - Real Time Interrupt Flag
1 (set)
–
A real time interrupt has occurred.
0 (clear) –
A real time interrupt has not occurred.
When RTIF is set, a CPU interrupt request is generated if RTIE is set. The clock frequency that
drives the RTI circuit is E/1213. The RTI rate is selectable by the RT1 and RT0 bits. RTIF is cleared
by writing a “0” to the bit.
CTOFE - CTimer Overow Interrupt Enable
1 (set)
–
TOF interrupt is enabled.
0 (clear) –
TOF interrupt is disabled.
RTIE - Real Time Interrupt Enable
1 (set)
–
Real time interrupt is enabled.
0 (clear) –
Real time interrupt is disabled.
RT1, RT0 - Rate Select for COP watchdog and RTI
See Section 6.2.3 on COP watchdog reset.
6.2.3
COP Watchdog Reset
The COP (Computer Operating Properly) watchdog timer function is implemented by using the
output of the RTI selected output. The minimum COP reset rates are determined by RT0 and RT1
of CTimer Control and Status register. If the COP circuit times out, an internal reset is generated
and the reset vector is fetched (at $3FFE & $3FFF). Preventing a COP time-out is achieved by
periodically writing a “0” to bit 0 of address $3FF0.
The COP reset function is enabled after a reset, and can be disabled by writing a “0” to the COP
bit (bit 6) in the Option Register at address $001D. Once disabled, it cannot be enabled except by
a reset function. Also, STOP mode cannot be entered when the COP watchdog is enabled.
Table 6-1 COP Reset and RTI Rates
RT1
RT0
Bus Frequency, fOP=2.1MHz
Divide Ratio
Minimum RTI Rate
Minimum COP Reset Rate (RTI x 7)
1/(fOP/Divide Ratio/7)
00
214
7.81ms
54.7ms
01
215
15.6ms
109ms
10
216
31.2ms
219ms
11
217
62.5ms
438ms
RT0 and RT1 should only be changed immediately after COP watchdog timer has been reset.
TPG
54
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