參數(shù)資料
型號: MC68HC05BS8FB
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PQFP44
封裝: QFP-44
文件頁數(shù): 110/128頁
文件大小: 752K
代理商: MC68HC05BS8FB
MOTOROLA
9-6
MC68HC05BS8
SYNC SIGNAL PROCESSOR
9
9.8
VSYNC Interrupt
The CPU will process an Sync Signal Processor VSYNC interrupt if the following conditions are
satised:
1) the I-bit of the CCR is cleared,
2) the VSIE bit of the Interrupt Line Count register (ILCR) is set, and
3) the value of the horizontal line counter matches the value set in the ILCR.
This interrupt will vector to the interrupt service routine located at the address specied by the
contents of $3FF8 and $3FF9. The VSYNC interrupt latch will be cleared automatically by fetching
of these vectors.
This allows an interrupt to be generated in each vertical frame after a certain number of lines
(0-127) to check the status of the monitor and conditions.
Figure 9-4 Vertical Frequency Counter Timing
PO2
VSYNC
Counter signal reset
PO2
÷ 64
case 1
PO2
÷ 64
case 2
Counter resets at 16 PO2 cycles
after falling edge of VSYNIN
Counter advances at the
rising edge of the clock
1. The value of the counter will be loaded into the register before it is reset.
2. The Vertical Frequency Counter is clocked by a PO2
÷ 64 clock.
3. Because of the asynchronous nature between PO2 and VSYNIN, the register
will have one more count in case 2 than in case 1.
TPG
80
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