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參數(shù)資料
| 型號(hào)： | MC68HC05BS8FB |
| 廠(chǎng)商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁(yè)數(shù)： | 111/128頁(yè) |
| 文件大?。?/td> | 752K |
| 代理商： | MC68HC05BS8FB |
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MC68HC05BS8
MOTOROLA
9-7
SYNC SIGNAL PROCESSOR
9
9.9
Sampling Pulse Output
The circuit is responsible for generating the SAM signal for the Video Chip set. The SAM signal is
a sampling signal, which outputs a positive pulse at the Vsync pulse, and outputs another positive
pulse when the value of the Sampling Pulse register matches the horizontal line counter. The
pulse width is equal to one horizontal line period.
9.10
SSP Registers
There are six registers associated with the Sync Signal Processor, these are described below.
9.10.1
Sync Signal Control and Status Register (SSCSR)
VPOL - Vertical Sync Input Polarity
1 (set)
–
VSYNC input is positive polarity.
0 (clear) –
VSYNC input is negative polarity.
Vertical Sync Input Polarity ag indicates the polarity of the incoming signal at the VSYNC input.
HPOL - Horizontal Sync Input Polarity
1 (set)
–
HSYNC input is positive polarity.
0 (clear) –
HSYNC input is negative polarity.
Horizontal Sync Input Polarity ag indicates the polarity of the incoming signal at the HSYNC
input.
VDET - Vertical Sync Signal Detect
1 (set)
–
An active vertical sync is detected at VSYNC input.
0 (clear) –
No vertical sync signal at VSYNC input; use internal generated
Vsync for VTTL.
This bit is set when an active vertical sync signal is detected on the VSYNC pin. If cleared, it
indicates there is no active signal, and the VTTL will output the internally generated Vsync signal.
An active vertical sync signal is dened as:
VDET = (VSYNC pulse width < 1024tCYC) (15.36x10
3t
CYC < VSYNC period < 48.128x10
3t
CYC)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$000A
VPOL
HPOL
VDET
HDET
SOUT
INSRT
SIN1
SIN0
0000 0000
TPG
81
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