參數(shù)資料
型號: MC68HC05BS8FB
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PQFP44
封裝: QFP-44
文件頁數(shù): 104/128頁
文件大?。?/td> 752K
代理商: MC68HC05BS8FB
MC68HC05BS8
MOTOROLA
9-1
SYNC SIGNAL PROCESSOR
9
SYNC SIGNAL PROCESSOR
This section describes the operation of the SSP module in the MC68HC05BS8.
9.1
Introduction
The functions of the SSP include the following:
Polarity correction
Sync separation
Sync pulse reshaping
Sync pulse detection
Horizontal line counting
Vertical frequency counting
Free running signals generation
In addition, an interrupt can be generated for each vertical frame at a user specied horizontal line
number. The SSP accepts composite signals from a video processor or separate sync inputs from
a host computer.
For separate sync inputs, the HTTL output is identical to the incoming horizontal sync with
negative sync polarity. The VTTL output is triggered by the leading edge of the incoming sync
pulse, and the sync pulse reshaper will correct the pulse width to a certain time period regardless
of the incoming sync width. Reassembled sync pulses are inserted for HTTL signal during the
vertical sync period for composite sync input.
The HSYNC, VSYNC, and CSYNC inputs have internal lters to improve noise immunity. Any
pulse that is shorter than 1.5 internal bus clock periods will be regarded as a glitch, and will be
ignored.
Note:
All quoted timings in this section are based on an internal bus frequency of 2MHz, i.e.
tCYC=0.5s, unless otherwise stated.
TPG
75
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