參數(shù)資料
型號: MC68HC05BS8FB
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PQFP44
封裝: QFP-44
文件頁數(shù): 101/128頁
文件大小: 752K
代理商: MC68HC05BS8FB
MOTOROLA
8-14
MC68HC05BS8
M-BUS SERIAL INTERFACE
8
is accomplished with MAL=1 and MSTA=0. If one master attempts to start transmission while the
bus is being controlled by another master, the transmission will be inhibited; the MSTA bit will be
changed from 1 to 0 without generating STOP condition; an interrupt will be generated and the
MAL bit set to indicate that the attempt to acquire the bus has failed. Considering these cases, the
slave service routine should test the MAL bit rst, and software should clear the MAL bit if it is set.
8.5
Software Supported M-Bus Interface
Port pins PC6 and PC7 are designed with a hardware interrupt circuit for the software supported
M-Bus interface to detect the “Start” condition of the M-Bus protocol. This interrupt uses the same
interrupt vector as for the hardware M-Bus interrupts, at address $3FF2 and $3FF3. The user is
responsible for determining the source of the M-Bus interrupt in the interrupt service routine by
reading the ags.
Figure 8-5 Software Supported M-Bus Interrupt
PC7/SDA2
PC6/SCL2
INT
D
C
R
Q
&
PC7/SDA2
PC6/SCL2
SIIC
Reset or SIFC
INT interrupt request
START
STOP
TPG
72
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