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參數(shù)資料
| 型號(hào)： | MC68HC05BS8FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 6/128頁 |
| 文件大?。?/td> | 752K |
| 代理商： | MC68HC05BS8FB |
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MC68HC05BS8
MOTOROLA
11-1
LOW POWER MODES
11
LOW POWER MODES
The MC68HC05BS8 has two low-power operating modes: the STOP mode and WAIT mode.
These two modes help to reduce the power required for the MCU by stopping various internal
clocks and/or the on-chip oscillator. The ow of the STOP and WAIT modes is shown in
11.1
STOP Mode
The STOP instruction places the MCU in its lowest power consumption mode. In the STOP mode
the internal oscillator is turned off, halting all internal processing.
When the CPU enters STOP mode, the I-bit in the Condition Code Register will be cleared
automatically. This enables the external hardware interrupt to “wake-up” the MCU. All other
registers and memory remain unchanged. All input/output lines remain unchanged.
The MCU can be brought out of the STOP mode only by a hardware interrupt or an externally
generated reset (POR or RESET). When exiting the STOP mode the internal oscillator will resume
after a 4064 internal processor clock cycle oscillator stabilization delay.
Note:
The STOP mode cannot be entered if the COP watchdog timer is running.
11.2
WAIT Mode
The WAIT instruction places the MCU in a low power mode. In the WAIT mode the internal
processor clock is halted, suspending all processor and internal bus activity. Other internal clocks
remain active, permitting interrupts to be generated from the sub-systems, or a reset generated
from the COP Watchdog Timer. The Timer may be used to generate a periodic exit from the WAIT
mode. Execution of the WAIT instruction automatically clears the I-bit in the Condition Code
Register, so that any hardware interrupt can “wake-up” the MCU. All other registers, memory, and
input/output lines remain in their previous states.
TPG
101
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