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| 型號(hào)： | MC68HC05BS8FB |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁(yè)數(shù)： | 73/128頁(yè) |
| 文件大?。?/td> | 752K |
| 代理商： | MC68HC05BS8FB |
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MC68HC05BS8
MOTOROLA
6-5
TIMERS
6
The two 8-bit registers that make up the 16-bit input capture register, are read-only, and are used
to latch the value of the free-running counter after the corresponding input capture edge detector
senses a valid transition. The level transition that triggers the counter transfer is dened by the
corresponding input edge bit (IEDG). Reset does not affect the contents of the input capture
register.
The result obtained from an input capture will be one greater than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition. This delay is
required for internal synchronization. Resolution is one count of the free-running counter, which is
four internal bus clock cycles.
The free-running counter contents are transferred to the input capture register on each valid signal
transition whether the input capture ag (ICF) is set or clear. The input capture register always
contains the free-running counter value that corresponds to the most recent input capture.After a
read of the input capture register MSB ($14), the counter transfer is inhibited until the LSB ($15)
is also read. This characteristic causes the time used in the input capture software routine and its
interaction with the main program to determine the minimum pulse period. A read of the input
capture register LSB ($15) does not inhibit the free-running counter transfer since they occur on
opposite edges of the internal bus clock.
6.1.4
Timer Control Register
The TCR is a read/write register containing ve control bits. Four bits control interrupts associated
with each of the four ag bits found in the Timer Status register. The other bit controls which edge
is signicant to the input capture edge detector. The Timer Control register and the free-running
counter are the only sections of the timer affected by reset.
Denition of each bit is as follows:
ICIE - Input Capture Interrupt Enable
1 (set)
–
Input Capture interrupt enabled.
0 (clear) –
Input Capture interrupt disabled.
OCIE - Output Compare Interrupt Enable
1 (set)
–
Output Compare interrupt enabled.
0 (clear) –
Output Compare interrupt disabled.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
TCR
$0012
ICIE
OCIE
TOIE
IEDG
OLVL 0000 00u1
TPG
47
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