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參數(shù)資料
| 型號： | MC68HC05BS8FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 44/128頁 |
| 文件大小： | 752K |
| 代理商： | MC68HC05BS8FB |
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MOTOROLA
2-2
MC68HC05BS8
PIN DESCRIPTION
2
2.2
Pin Assignment
PB0-PB7
25-18
These eight I/O lines comprise port B. The state of any pin is software
programmable. All port B lines are congured as input during power-on or external
reset.
PB7 is also used as the RSPWM counter reset input when PB7 is set as an input
pin and the counter reset enable bit is set in the GPWM register (bit 6 of $0010).
PC0-PC7
17-10
These eight I/O lines comprise port C. The state of any pin is software
programmable. All port C lines are congured as input during power-on or external
reset.
PC0-PC5 become keyboard interrupt input pins when the corresponding bits are
set in the Keyboard Interrupt register ($001E).
PC6 and PC7 are SDA and SCL respectively, when used for the software
supported M-Bus Interface.
SDA, SCL
2, 3
These are the hardware M-Bus interface data and clock lines.
TCAP
9
This input pin controls the input capture function of the 16-bit free-running timer.
TCMP
8
This output pin indicates when a timer compare is successful.
GPWM
7
This is the output pin of the General purpose PWM.
RSA, RSB
5, 6
These are the two excursive outputs of the Raster Positioning PWM
RCLK
4
This is the input clock to drive the RSPWM counter.
HSYNC, VSYNC
40, 41
These two input pins are for the video sync signals from the host computer.
CSYNC
42
This is the Composite sync signal input from the host computer.
SAM
43
This is the output of an sample signal from the Sync Signal Processor.
HTTL, VTTL
44, 1
These are the output from the HSYNC and VSYNC inputs or the signals separated
from CSYNC input.
Figure 2-1 Pin Assignment for 44-pin QFP Package
PIN NAME
44-pin QFP
PIN No.
DESCRIPTION
IRQ
RESET
OSC2
12
13
15
16
17
18
19
20
21
22
14
33
32
30
29
28
27
26
25
24
23
31
PA0
PA1
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PA2
VTTL
SDA
RCLK
RSA
RSB
GPWM
TCMP
TCAP
PC7
PC6
SCL
PC5
PC4
PC2
PC1
PC0
PB7
PB5
PB4
PB3
PC3
HTTL
SAM
VSYNC
HSYNC
VSS
VDD
OSC1
CSYNC
1
2
4
5
6
7
8
9
10
11
3
PB6
44
43
41
40
39
38
36
35
34
42
37
TPG
20
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