參數(shù)資料
型號： MC68HC05BS8FB
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PQFP44
封裝： QFP-44
文件頁數(shù)： 75/128頁
文件大?。?/td> 752K
代理商： MC68HC05BS8FB
MOTOROLA
6-6
MC68HC05BS8
TIMERS
6
TOIE - Timer Overow Interrupt Enable
1 (set)
–
Timer Overow interrupt enabled.
0 (clear) –
Timer Overow interrupt disabled.
IEDG - Input Edge
1 (set)
–
TCAP is positive-going edge sensitive.
0 (clear) –
TCAP is negative-going edge sensitive.
When IEDG is set, a positive-going edge on the TCAP pin will trigger a transfer of the free-running
counter value to the input capture registers. When clear, a negative-going edge triggers the
transfer.
OLVL - Output Level Voltage Latch
1 (set)
–
High output on TCMP pin if counter compare is true.
0 (clear) –
Low output on TCMP pin if counter compare is true.
When OLVL is set high output level will be clocked into the output level register by the next
successful output compare on the TCMP pin.
6.1.5
Timer Status Register (TSR)
The Timer Status register contains the status bits for the above three interrupt conditions - ICF,
OCF, and TOF.
Accessing the timer status register satises the rst condition required to clear the status bits. The
remaining step is to access the register corresponding to the status bit.
ICF - Input Capture Flag
1 (set)
–
A valid input capture has occurred.
0 (clear) –
No input capture has occurred.
This bit is set when the selected polarity of edge is detected by the input capture edge detector;
an input capture interrupt will be generated, if ICIE is set, ICF is cleared by reading the TSR and
then the Input Capture Low register ($15)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
TSR
$0013
ICF
OCF
TOF
0
uuu0 0000
TPG
48
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