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參數(shù)資料
| 型號(hào)： | MC68HC05BS8FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 65/128頁 |
| 文件大小： | 752K |
| 代理商： | MC68HC05BS8FB |
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MC68HC05BS8
MOTOROLA
5-7
RESETS AND INTERRUPTS
5
next pulse should not occur until the MCU software has exited the routine (an RTI occurs). The
second conguration shows several interrupt lines wired-OR to perform the interrupt at the
processor. Thus, if the interrupt lines remain low after servicing one interrupt, the next interrupt is
recognized.
Note:
The internal interrupt latch is cleared in the rst part of the service routine; therefore,
one (and only one) external interrupt pulse could be latched during tILIL and serviced
as soon as the I-bit is cleared.
5.2.2.2
Sync Signal Processor Interrupt
The CPU will process an Sync Signal Processor VSYNC interrupt if the following conditions are
satised:
1) the I-bit of the CCR is cleared,
2) the VSIE bit of the Interrupt Line Count register (ILCR) is set, and
3) the value of the horizontal line counter matches the value set in the ILCR.
This interrupt will vector to the interrupt service routine located at the address specied by the
contents of $3FF8 and $3FF9. The VSYNC interrupt latch will be cleared automatically by fetching
of these vectors.
Refer to Section 9 for detailed description of Sync Signal Processor.
5.2.2.3
M-Bus Interrupts
The hardware M-Bus interrupt is enabled when the M-Bus Interrupt Enable bit (MIEN) of M-Bus
Control register is set, provided the interrupt mask bit of the Condition Code register is cleared.
The interrupt service routine address is specied by the contents of memory location $3FF2 and
$3FF3.
MIF - M-Bus Interrupt
1 (set)
–
An M-Bus interrupt has occurred.
0 (clear) –
An M-Bus interrupt has not occurred.
When this bit is set, an interrupt is generated to the CPU if MIEN is set. This bit is set when one
of the following events occurs:
1) Completion of one byte of data transfer. It is set at the falling edge of the 9th
clock - MCF set.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
M-Bus Status Register
$001A
MCF
MAAS
MBB
MAL
SIF
SRW
MIF
RXAK 1000 0001
TPG
39
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