參數(shù)資料
型號： MC68HC05BS8FB
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PQFP44
封裝： QFP-44
文件頁數(shù)： 62/128頁
文件大小： 752K
代理商： MC68HC05BS8FB
MC68HC05BS8
MOTOROLA
5-5
RESETS AND INTERRUPTS
5
5.2.1
Non-maskable Software Interrupt (SWI)
The software interrupt (SWI) is an executable instruction and a non-maskable interrupt: it is
execute regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupt enabled), SWI
is executed after interrupts that were pending when the SWI was fetched, but before interrupts
generated after the SWI was fetched. The SWI interrupt service routine address is specied by
the contents of memory locations $3FFC and $3FFD.
5.2.2
Maskable Hardware Interrupts
If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts (internal and external) are
masked. Clearing the I-bit allows interrupt processing to occur.
Note:
The internal interrupt latch is cleared in the rst part of the interrupt service routine;
therefore, one external interrupt pulse could be latched and serviced as soon as the
I-bit is cleared.
5.2.2.1
External Interrupt (IRQ)
The external interrupt IRQ can be software congured for “negative-edge” or “negative-level”
sensitive triggering by the INTO bit in the Option register.
INTO
1 (set)
–
Negative-edge sensitive triggering for IRQ.
0 (clear) –
Negative-level sensitive triggering for IRQ.
When the signal of the external interrupt pin, IRQ, satises the condition selected, an external
interrupt occurs. The actual processor interrupt is generated only if the interrupt mask bit of the
condition code register is also cleared. When the interrupt is recognized, the current state of the
processor is pushed onto the stack and the interrupt mask bit in the condition code register is set.
This masks further interrupts until the present one is serviced. The service routine address is
specied by the contents $3FFA & $3FFB.
The interrupt logic recognizes negative edge transitions and pulses (special case of negative
edges) on the external interrupt line. Figure 5-3 shows both a block diagram and timing for the
interrupt line (IRQ) to the processor. The rst method is used if pulses on the interrupt line are
spaced far enough apart to be serviced. The minimum time between pulses is equal to the number
of cycles required to execute the interrupt service routine plus 21 cycles. Once a pulse occurs, the
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Option register
$001D
INTO
COP
01-- ----
TPG
37
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