參數(shù)資料
型號： MC68HC05BS8FB
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PQFP44
封裝： QFP-44
文件頁數(shù)： 79/128頁
文件大?。?/td> 752K
代理商： MC68HC05BS8FB
MOTOROLA
6-10
MC68HC05BS8
TIMERS
6
6.2
CORE TIMER
The Core Timer is a 15-stage multi-functional ripple counter which provides miscellaneous
function to the MC68HC05BS8 MCU. It includes a timer overow function, real-time interrupt, and
COP watchdog.
As seen in Figure 6-6, the Timer is driven by the internal bus clock divided by four with a xed
prescaler. This signal drives an 8-bit ripple counter. The value of this 8-bit ripple counter can be
read by the CPU at any time by accessing the Ctimer Counter register (CTCR) at address $09. A
timer overow function is implemented on the last stage of this counter, giving a possible interrupt
at the rate of E/1024. Four additional stages produces a resulting clock of E/16384, driving the
Real Time Interrupt circuit. The RTI circuit consists of three divider stages with a 1 of 4 selector.
The output of the RTI circuit is further divided by eight to drive the optional COP Watchdog Timer
circuit. The RTI rate selector bits, and the RTI and CTOF enable bits and ags are located in the
CTimer Control and Status register (CTCSR) at location $08.
6.2.1
CTimer Counter Register
The Core Timer Counter register is a read-only register which contains the current value of the
8-bit ripple counter. This counter is clocked at fOP/4 and can be used for various functions including
a software capture. Extended time periods can be attained using the TOF function to increment a
temporary RAM storage location thereby simulating a 16-bit (or more) counter.
During the Power-on reset (POR) cycle, all CTimer counters are rst cleared, the counters then
count 4064 cycles before it is cleared again. After this 4064 cycles, the POR circuit releases the
device from reset. At this point, if RESET is not asserted, the timer will start counting up from zero
and normal device operation will begin. If RESET is asserted anytime during operation (other than
POR), the counter chain will be cleared.
6.2.2
CTimer Control and Status Register
CTOF - CTimer Overow
1 (set)
–
8-bit ripple timer overow has occurred.
0 (clear) –
No 8-bit ripple timer overow has occurred.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
CTCR
$0009
CT7
CT6
CT5
CT4
CT3
CT2
CT1
CT0
0000 0000
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
CTCSR
$0008
CTOF
RTIF CTOFE RTIE
0
RT1
RT0
0000 0011
TPG
52
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