參數(shù)資料
型號： MC68HC05BS8FB
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PQFP44
封裝： QFP-44
文件頁數(shù)： 72/128頁
文件大?。?/td> 752K
代理商： MC68HC05BS8FB
MOTOROLA
6-4
MC68HC05BS8
TIMERS
6
6.1.2
Output Compare Register
The 16-bit Output Compare register is used for several purposes, such as indicating when a period
of time has elapsed. All bits are readable and writable and are not affected by the timer hardware
or reset. If the compare function is not needed, the Output Compare register can be used as
storage locations.
The contents of the Output Compare register are continually compared with the contents of the
free-running counter and, if a match is found, the output compare ag (OCF) in the Timer Status
register is set. The Output Compare register’ value should be changed after each successful
comparison to establish a new elapsed time-out. An interrupt can also accompany a successful
output compare provided the interrupt enable bit (OCIE) is set. (The free-running counter is
updated every four internal bus clock cycles.)
After a processor write cycle to the Output Compare register containing the MSB ($16), the output
compare function is inhibited until the LSB ($17) is also written. The user must write both bytes
(locations) if the MSB is written rst. A write made only to the LSB ($17) will not inhibit the compare
function. The processor can write to either byte of an Output Compare register without affecting
the other byte. The minimum time required to update the Output Compare register is a function of
the program rather than the internal hardware. Because the output compare ag and Output
Compare register are not dened at power on, and not affected by reset, care must be taken when
initializing output compare functions with software. The following procedure is recommended:
1) write to Output Compare register High-byte to inhibit further compares;
2) read the Timer Status register to initialize clearing of OCF;
3) write to Output Compare register Low-byte to enable the output compare
function.
6.1.3
Input Capture Registers
‘Input Capture’ is a technique whereby an external signal (connected to TCAP pin) is used to
trigger a read of the free-running counter. In this way it is possible to relate the timing of an external
signal to the internal counter value, and hence to elapsed time.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
OCMPH
$0016
OC15
OC14
OC13
OC12
OC11
OC10
OC9
OC8
unaffected
OCMPL
$0017
OC7
OC6
OC5
OC4
OC3
OC2
OC1
OC0
unaffected
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
ICAPH
$0014
IC15
IC14
IC13
IC12
IC11
IC10
IC9
IC8
unaffected
ICAPL
$0015
IC7
IC6
IC5
IC4
IC3
IC2
IC1
IC0
unaffected
TPG
46
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